User controlled data-in for lower and middle page in MLC-fine QLC memories
Aspects of a storage device including a memory and a controller are provided. The memory includes non-volatile memory and volatile memory. The controller may determine whether first data is available at a system-level memory location during a first programming stage of a two-stage programming sequence. The controller may read the first data from the system-level memory location when the page data is available at the system-level memory location. Alternatively, the controller may read the first data from the non-volatile memory when the page data is not available at the system-level memory location. Thus, the controller may perform a first programming operation associated with the first programming stage using the first data, thereby improving memory programming performance of the storage device.
1. A storage device, comprising:
a memory including non-volatile memory and volatile memory; and
a controller configured to:
determine whether first data is available at a system-level memory location during a first programming stage of a two-stage programming sequence that corresponds to fine programming, wherein the first data is written to the memory with a second programming stage of the two-stage programming sequence that corresponds to foggy programming comprising a multi-level cell (MLC) write operation;
read the first data from the system-level memory location when the first data is available at the system-level memory location;
read the first data from the non-volatile memory when the first data is not available at the system-level memory location; and
perform a first programming operation associated with the first programming stage using the first data.
2. The storage device of claim 1 , wherein the controller is configured to transition into the first programming stage from the second programming stage of the two-stage programming sequence.
3. The storage device of claim 2 , wherein the second programming stage is initiated with two pages of data.
4. The storage device of claim 1 , wherein the two-stage programming sequence includes a programming order that corresponds to a foggy-fine programming sequence.
5. The storage device of claim 1 , wherein the controller is configured to start the first programming stage using the first data and second data.
6. The storage device of claim 5 , wherein the first data comprises lower page data and middle page data and the second data comprises upper page data and top page data.
7. The storage device of claim 1 , wherein the controller is configured to send an indication that the first data is being supplied from the system-level memory location and that the first data is not to be sensed internally from the non-volatile memory as part of the first programming operation.
8. The storage device of claim 7 , wherein the indication comprises a command prefix that indicates a command to the non-volatile memory to refrain from performing an internal sense operation for the first data as part of the first programming operation.
9. The storage device of claim 1 , wherein the system-level memory location corresponds to a memory location in a single-level cell (SLC) block of the non-volatile memory.
10. The storage device of claim 1 , wherein the system-level memory location corresponds to a memory location in the volatile memory.
11. The storage device of claim 1 , wherein the system-level memory location corresponds to a memory location in a host memory buffer at a host device.
12. A storage device, comprising:
a memory including non-volatile memory and volatile memory; and
a controller configured to:
transition into a first programming stage of a two-stage programming sequence that corresponds to fine programming from a second programming stage of the two-stage programming sequence that corresponds to foggy programming comprising a multi-level cell (MLC) write operation;
determine whether first data is available at a system-level memory location during the first programming stage;
read the first data from the system-level memory location when the first data is available at the system-level memory location;
read the first data from the non-volatile memory when the first data is not available at the system-level memory location; and
perform a first programming operation associated with the first programming stage using the first data.
13. The storage device of claim 12 , wherein the controller is configured to send an indication that the first data is being supplied from the system-level memory location and that the first data is not to be sensed internally from the non-volatile memory as part of the first programming operation.
14. The storage device of claim 13 , wherein the indication comprises a command prefix that indicates a command to the non-volatile memory to refrain from performing an internal sense operation for the first data as part of the first programming operation.
15. The storage device of claim 12 , wherein the system-level memory location corresponds to a memory location in a single-level cell (SLC) block of the non-volatile memory.
16. The storage device of claim 12 , wherein the system-level memory location corresponds to a memory location in the volatile memory.
17. The storage device of claim 12 , wherein the system-level memory location corresponds to a memory location in a host memory buffer at a host device.
18. A storage device, comprising:
a memory including non-volatile memory and volatile memory; and
a controller configured to:
transition into a first programming stage of a two-stage programming sequence that corresponds to fine programming from a second programming stage of the two-stage programming sequence that corresponds to foggy programming comprising a multi-level cell (MLC) write operation;
determine whether first data is available at a system-level memory location during the first programming stage;
read the first data from the system-level memory location when the first data is available at the system-level memory location;
send an indication that the first data is being supplied from the system-level memory location as part of the first programming stage; and
perform a first programming operation associated with the first programming stage using the first data.
19. The storage device of claim 18 , wherein the controller is configured to read the first data from the non-volatile memory when the first data is not available at the system-level memory location.
20. The storage device of claim 18 , wherein the indication comprises a command prefix further that indicates a command to the non-volatile memory to refrain from performing an internal sense operation for the first data as part of the first programming stage.