IP Library Granted Patent US 11,031,372
Granted Patent B2
US 11,031,372 · App. 16/398,511 · Granted Jun 8, 2021

Semiconductor device including dummy pull-down wire bonds

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Quick Facts
Patent No.
US 11,031,372
App. No.
16/398,511
Granted
Jun 8, 2021
Kind
B2
Abstract

A semiconductor device is disclosed including a stack of semiconductor die on a substrate, wherein a semiconductor die in the stack is wire bonded to the substrate using dummy wire bonds. Each dummy wire bond has a stiffness so that together, the dummy wire bonds effectively pull and/or hold down the die stack against the substrate.

Claims (37)

1. A semiconductor device, comprising:

a substrate including a set of contact pads;

one or more semiconductor die mounted on the substrate and electrically coupled to the substrate, at least one semiconductor die of the one or more semiconductor die comprising a set of bond pads; and

a set of wire bonds connected between the set of bond pads on the at least one semiconductor die and the set of contact pads on the substrate, the set of wire bonds configured to exert a force on the one or more semiconductor die to hold the one or more semiconductor die down on the substrate.

2. The semiconductor device of claim 1 , wherein the one or more semiconductor die comprise a plurality of stacked semiconductor die, and wherein the at least one semiconductor die comprises a topmost semiconductor die in the plurality of stacked semiconductor die.

3. The semiconductor device of claim 1 , wherein the set of wire bonds comprise a first set of wire bonds, and wherein the one or more semiconductor die are electrically coupled to the substrate by a second set of wire bonds different than the first set of wire bonds.

4. The semiconductor device of claim 3 , wherein there are more wire bonds in the second set of wire bonds than there are in the first set of wire bonds.

5. The semiconductor device of claim 1 , wherein the set of contact pads on the substrate are aligned in a single row.

6. The semiconductor device of claim 5 , wherein the single row of contact pads are adjacent an edge of the substrate.

7. The semiconductor device of claim 1 , wherein the set of contact pads on the substrate are aligned in two or more rows.

8. The semiconductor device of claim 1 , wherein the set of die bond pads comprise a set of dummy bond pads, and wherein the one or more semiconductor die comprise a plurality of semiconductor die stacked in an offset stepped arrangement, the semiconductor device further comprising a set of signal transfer bond pads on a portion of each semiconductor die exposed by the offset stepped arrangement.

9. The semiconductor device of claim 8 , wherein the set of wire bonds comprise a set of dummy wire bonds, the semiconductor device further comprising a set of signal transfer wire bonds coupled to the signal transfer bond pads of the plurality of semiconductor die.

10. The semiconductor device of claim 9 , wherein the set of contact pads on the substrate comprise a first set of contact pads, the semiconductor device further comprising a second set of contact pads electrically coupled to the signal transfer bond pads by the signal transfer wire bonds.

11. The semiconductor device of claim 8 , further comprising a controller die mounted on the substrate beneath one or more of the plurality of semiconductor die stacked in the offset stepped arrangement.

12. The semiconductor device of claim 1 , wherein the one or more semiconductor die comprise a plurality of semiconductor die stacked in an offset stepped arrangement, and the at least one semiconductor die comprises a topmost semiconductor die on the stack, the semiconductor device further comprising a controller die mounted on the substrate beneath the topmost semiconductor die in the stack.

13. The semiconductor device of claim 12 , wherein an area of the topmost semiconductor die above the controller die is devoid of bond pads.

14. A semiconductor device, comprising:

a substrate including a first set of contact pads and a second set of contact pads;

one or more semiconductor die mounted on the substrate, at least one semiconductor die of the one or more semiconductor die comprising a first set of bond pads and a second set of bond pads;

a first set of wire bonds electrically connecting the first set of bond pads on the at least one semiconductor die to the first set of contact pads on the substrate, the first set of wire bonds configured to transfer signals between the first set of bond pads and the first set of contact pads; and

a second set of wire bonds connected between the second set of bond pads on the at least one semiconductor die and the second set of contact pads on the substrate, the second set of wire bonds configured to exert a force on the one or more semiconductor die to hold the one or more semiconductor die down on the substrate.

15. The semiconductor device of claim 14 , wherein the first set of wire bonds extend off a first edge of the at least one semiconductor die, and the second set of wire bonds extend off a second, opposed edge of the at least one semiconductor die.

16. The semiconductor device of claim 14 , wherein the one or more semiconductor die comprise a plurality of offset stacked semiconductor die stepped in a first direction.

17. The semiconductor device of claim 16 , wherein the at least one semiconductor die is a topmost semiconductor die in the stack.

18. The semiconductor device of claim 16 , wherein the plurality of semiconductor die comprise a first plurality of semiconductor die, and wherein the one or more semiconductor die comprise a second plurality of offset stacked semiconductor die stepped in a second direction opposite to the first direction.

19. The semiconductor device of claim 18 , wherein the at least one semiconductor die is positioned between the first and second pluralities of semiconductor die.

20. A semiconductor device, comprising:

a substrate including a first set of contact pads and a second set of contact pads;

a plurality of semiconductor die stacked on the substrate in an offset stepped arrangement;

a component mounted on top of the plurality of semiconductor die;

a set of dummy bond pads formed along an edge of the component;

a set of signal transfer wire bonds configured to electrically connect the plurality of semiconductor die with each other and the first set of contact pads on the substrate; and

a set of dummy wire bonds connected between the set of dummy bond pads and the second set of contact pads on the substrate, the set of dummy wire bonds configured to exert a force on the plurality of semiconductor die to hold the plurality of semiconductor die down on the substrate.

21. The semiconductor device of claim 20 , wherein the component is devoid of integrated circuits.

22. The semiconductor device of claim 20 , wherein the component comprises a semiconductor die comprising integrated circuits.

23. The semiconductor device of claim 22 , wherein the component further comprises a set of signal transfer bond pads along an edge of the component opposed to the edge including the set of dummy bond pads.

24. The semiconductor device of claim 23 , wherein the component is electrically coupled to the substrate via the set of signal transfer wire bonds connected to the set of signal transfer bond pads.

Assignments (10)
PARTIAL RELEASE OF SECURITY INTERESTS Recorded Apr 25, 2025
From: JPMORGAN CHASE BANK, N.A., AS AGENT
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 071382/0001 →
SECURITY AGREEMENT Recorded Apr 25, 2025
From: SANDISK TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 071050/0001 →
PATENT COLLATERAL AGREEMENT Recorded Aug 23, 2024
From: SANDISK TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS THE AGENT
Reel/Frame 068762/0494 →
CHANGE OF NAME Recorded Jun 27, 2024
From: SANDISK TECHNOLOGIES, INC.
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 067982/0032 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 29, 2024
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 067567/0682 →
PATENT COLLATERAL AGREEMENT - DDTL LOAN AGREEMENT Recorded Aug 21, 2023
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A.
Reel/Frame 067045/0156 →
PATENT COLLATERAL AGREEMENT - A&R LOAN AGREEMENT Recorded Aug 21, 2023
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A.
Reel/Frame 064715/0001 →
RELEASE OF SECURITY INTEREST AT REEL 057651 FRAME 0296 Recorded Feb 8, 2022
From: JPMORGAN CHASE BANK, N.A.
To: WESTERN DIGITAL TECHNOLOGIES, INC.
Reel/Frame 058981/0958 →
SECURITY INTEREST Recorded Sep 17, 2021
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS AGENT
Reel/Frame 057651/0296 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 14, 2019
From: CHEN, HAN-SHIAO; LIAO, CHIH-CHIN; CHIU, CHIN-TIEN
To: WESTERN DIGITAL TECHNOLOGIES, INC.
Reel/Frame 049177/0072 →