IP Library Granted Patent US 10,685,722
Granted Patent B1
US 10,685,722 · App. 16/256,010 · Granted Jun 16, 2020

Method and system for improving performance of a storage device using asynchronous independent plane read functionality

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Quick Facts
Patent No.
US 10,685,722
App. No.
16/256,010
Granted
Jun 16, 2020
Kind
B1
Abstract

In one embodiment there is a method for calculating a timer at a storage device including a plurality of memory portions for storing data and a memory controller for performing operations on the memory portions, the method comprises receiving a request to perform an initial operation on a memory portion; determining an operational characteristic associated with the initial operation to be performed on the memory portion; and calculating an amount of time for a memory portion timer based on the operational characteristics before the initiation of the initial operation on the memory portion, wherein performance of a subsequent operation for another memory portion is delayed until the amount of time for the memory portion timer has elapsed since initiation of the operation on the memory portion.

Claims (18)

1. A data storage system for implementing independent memory portion reads, the data storage system comprising:

a memory controller for performing operations on one or more memory portions for storing data, the memory controller configured to perform the steps of:

receiving a request to perform a first operation on a first memory portion;

determining, for a second memory portion, whether a second memory portion timer having a respective amount of time has elapsed since initiation of a second operation being performed on the second memory portion, separate and distinct from the first memory portion;

in response to a determination that the respective amount of time for the second memory portion timer has not elapsed:

delay performing the first operation on the first memory portion until the respective amount of time associated with initiation of the second operation performed on the second memory portion has elapsed, and

after delaying performance, performing the first operation on the first memory portion while the second operation continues to be performed on the second memory portion; and

in response to a determination that the respective amount of time for the second memory portion timer has elapsed, performing the first operation on the first memory portion.

2. The data storage system of claim 1 , wherein the memory controller is further configured to perform the operation of:

before performing the second operation on the second memory portion:

determining a respective operational characteristic of the second operation to be performed on the second memory portion; and

calculating the respective amount of time for the second memory portion timer based on the respective operational characteristic of the second operation to be performed on the second memory portion.

3. The data storage system of claim 2 , wherein the respective operational characteristic of the second operation is at least one of: memory characteristics, page combination characteristics and sensing operation characteristics of the respective memory portion.

4. The data storage system of claim 3 , wherein the operational characteristic is a memory characteristic that includes at least one of: program/erase cycle, data retention, cross-temperature, system temperature and read-disturb.

5. The data storage system of claim 1 , wherein the memory controller is further configured to perform the operation of:

in response to performance of the first operation on the first memory portion, initializing a first memory portion timer including a respective amount of time to perform the first operation on the first memory portion.

6. The data storage system of claim 1 , wherein the first memory portion and the second memory portion are connected to a same power source.

7. The data storage system of claim 1 , wherein the first memory portion and the second memory portion are at least one of: a plane, a die, a block, and a page.

Assignments (10)
SECURITY AGREEMENT Recorded Apr 25, 2025
From: SANDISK TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 071050/0001 →
PARTIAL RELEASE OF SECURITY INTERESTS Recorded Apr 25, 2025
From: JPMORGAN CHASE BANK, N.A., AS AGENT
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 071382/0001 →
PATENT COLLATERAL AGREEMENT Recorded Aug 23, 2024
From: SANDISK TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS THE AGENT
Reel/Frame 068762/0494 →
CHANGE OF NAME Recorded Jun 27, 2024
From: SANDISK TECHNOLOGIES, INC.
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 067982/0032 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 29, 2024
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 067567/0682 →
PATENT COLLATERAL AGREEMENT - A&R LOAN AGREEMENT Recorded Aug 21, 2023
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A.
Reel/Frame 064715/0001 →
PATENT COLLATERAL AGREEMENT - DDTL LOAN AGREEMENT Recorded Aug 21, 2023
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A.
Reel/Frame 067045/0156 →
RELEASE OF SECURITY INTEREST AT REEL 052915 FRAME 0566 Recorded Feb 8, 2022
From: JPMORGAN CHASE BANK, N.A.
To: WESTERN DIGITAL TECHNOLOGIES, INC.
Reel/Frame 059127/0001 →
SECURITY INTEREST Recorded Feb 6, 2020
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS AGENT
Reel/Frame 052915/0566 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 28, 2019
From: YANG, NILES; SHARMA, SAHIL; REUSSWIG, PHIL; SEHGAL, ROHIT
To: WESTERN DIGITAL TECHNOLOGIES, INC.
Reel/Frame 048158/0594 →