IP Library Granted Patent US 11,557,350
Granted Patent B2
US 11,557,350 · App. 17/211,602 · Granted Jan 17, 2023

Dynamic read threshold calibration

Inventors: Alexander Bazarsky (Holon, IL); Eran Sharon (Rishon Lezion, IL); Idan Alrod (Herzliya, IL)
Assignee: Western Digital Technologies, Inc.
G11C16/26G06F11/1068G11C11/5642
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Quick Facts
Patent No.
US 11,557,350
App. No.
17/211,602
Granted
Jan 17, 2023
Kind
B2
Abstract

A method and apparatus for calibrating read threshold for cells of a target wordline (WL) that may be conducted on a die, in a controller connected to a memory die, or both. Voltage values of one or more adjacent WL cells are read, and based on the voltage values of the adjacent cells, cells of the target WL are grouped. A read threshold calibration is carried out on each group. The calibration thresholds are then used for read operations on the cells of each distinct group of the target WL.

Claims (61)

1. A data storage device, comprising:

a non-volatile memory (NVM); and

a controller coupled to the NVM and configured to execute a method for memory cell read calibration, the method comprising:

identify a first cell of a plurality of cells of a target wordline (WL) of the NVM;

read a voltage of a first adjacent cell of an adjacent WL, physically adjacent to the first cell; and

calibrating a first read threshold of the first cell based on the voltage, wherein the calibrating comprises:

reading a plurality of voltages for the target WL, wherein the plurality of voltages are a first curve, and second curve, and a third curve; wherein the first curve is a voltage status of all memory cells of the target WL; wherein the second curve is a voltage status of the target WL according to the adjacent WL at a low reading; wherein the third curve is a voltage status of the target WL according to the adjacent WL at a high reading; and wherein an intersection of each signal represented by the curves reflects a minima of the first read threshold.

2. The data storage device of claim 1 , the method further comprising:

identifying a second cell of the plurality of cells;

reading a second voltage of a second adjacent cell of the adjacent WL, physically adjacent to the second cell; and

calibrating a second read threshold of the second cell based on the second voltage.

3. The data storage device of claim 2 , wherein the second read threshold is different from the first read threshold.

4. The data storage device of claim 3 , the method further comprising performing a read operation on the first cell based on the first read threshold and the second cell based on the second read threshold.

5. The data storage device of claim 1 , the method further comprising:

reading a target voltage from the first cell; and

correcting the target voltage based on the voltage.

6. The data storage device of claim 5 , the method further comprising:

identifying a read error in the target voltage using an error correction code (ECC).

7. The data storage device of claim 6 , further comprising applying a READ voltage at the first cell.

8. A controller for a data storage device, comprising:

an I/O to one or more non-volatile memories (NVMs); and

a processor configured to perform a method for dynamic read threshold calibration of one or more memory cells of the one or more NVM, the method comprising:

reading a first voltage of a first group of cells from a first wordline (WL) of the one or more NVMs;

classifying a second group of cells of a second WL of the one or more NVMs based on the first voltage; and

calibrating the second group of cells based on the first voltage with a first calibrated read threshold, wherein the first calibrated read threshold is determined by:

reading a plurality of voltages for the first WL, wherein the plurality of voltages are a first curve, and second curve, and a third curve; wherein the first curve is a voltage status of all memory cells of the first WL; wherein the second curve is a voltage status of the first WL according to an adjacent WL at a low reading; wherein the third curve is a voltage status of the first WL according to the adjacent WL at a high reading; and wherein an intersection of each signal represented by the curves reflects a minima of the first calibrated read threshold.

9. The controller of claim 8 , the method further comprising:

reading a second voltage from a third group of cells from the first WL;

classifying a fourth group of cells of the second WL; and

calibrating the fourth group of cells based on the second voltage with a second calibrated read threshold.

10. The controller of claim 9 , wherein calibrating the second group and the fourth group further comprises:

receiving a read command for data of the second WL; and

applying the first calibrated read threshold and second calibrated read threshold to the second group of cells and the fourth group of cells, respectively.

11. The controller of claim 9 , the method further comprising applying the first calibrated read threshold and second calibrated read threshold at approximately the same time, and reading from the second group of cells and fourth group of cells in parallel.

12. The controller of claim 9 , the method further comprising:

detecting a regular decoding failure; and

performing a look-ahead read on the first group of cells and the second group of cells.

13. The controller of claim 12 , wherein the look-ahead comprises:

reading the first voltage and second voltage from the first group of cells and third group of cells; and

reading a third voltage from the second group of cells based on the first voltage and second voltage.

14. The controller of claim 13 , the method further comprising identifying an error in the third voltage.

15. A system for storing data, comprising:

a non-volatile memory means; and

a controller comprising a processor and memory comprising computer-readable instructions for executing a method for dynamic read calibration, the controller coupled to the non-volatile memory means, the method comprising:

measuring a first voltage from a first group of cells of a first wordline (WL);

measuring a second voltage from a second group of cells of a second WL adjacent the first WL, equalizing the second voltage based on the first voltage;

detecting an error in the second voltage; and

calibrating a read threshold of the second voltage based on the first voltage, wherein the calibrating comprises:

reading a plurality of voltages for a target WL, wherein the plurality of voltages are a first curve, and second curve, and a third curve; wherein the first curve is a voltage status of all memory cells of the target WL; wherein the second curve is a voltage status of the target WL according to an adjacent WL at a low reading; wherein the third curve is a voltage status of the target WL according to the adjacent WL at a high reading; and wherein an intersection of each signal represented by the curves reflects a minima of the read threshold.

16. The system of claim 15 , the method further comprising:

measuring a third voltage from a third group of cells of the first WL; and

measuring a fourth voltage from a fourth group of cells of the second WL.

17. The system of claim 16 , the method further comprising:

calibrating a second read threshold of the fourth voltage based on the third voltage.

18. The system of claim 17 , the method further comprising:

receiving a read request from a host for the second group of cells and fourth group of cells; and

reading a plurality of voltages from the second and fourth group of cells using the calibrated read threshold and second calibrated read threshold.

19. The system of claim 18 , the method further comprising:

measuring a fifth voltage of a fifth group of cells of a third WL, the third WL adjacent the second WL.

20. The system of claim 19 , the method further comprising:

calibrating a third read threshold of the second voltage based on the fifth voltage.

Assignments (10)
PARTIAL RELEASE OF SECURITY INTERESTS Recorded Apr 25, 2025
From: JPMORGAN CHASE BANK, N.A., AS AGENT
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 071382/0001 →
SECURITY AGREEMENT Recorded Apr 25, 2025
From: SANDISK TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 071050/0001 →
PATENT COLLATERAL AGREEMENT Recorded Aug 23, 2024
From: SANDISK TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS THE AGENT
Reel/Frame 068762/0494 →
CHANGE OF NAME Recorded Jun 27, 2024
From: SANDISK TECHNOLOGIES, INC.
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 067982/0032 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 29, 2024
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 067567/0682 →
PATENT COLLATERAL AGREEMENT - DDTL LOAN AGREEMENT Recorded Aug 21, 2023
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A.
Reel/Frame 067045/0156 →
PATENT COLLATERAL AGREEMENT - A&R LOAN AGREEMENT Recorded Aug 21, 2023
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A.
Reel/Frame 064715/0001 →
RELEASE OF SECURITY INTEREST AT REEL 056285 FRAME 0292 Recorded Feb 8, 2022
From: JPMORGAN CHASE BANK, N.A.
To: WESTERN DIGITAL TECHNOLOGIES, INC.
Reel/Frame 058982/0001 →
SECURITY INTEREST Recorded May 19, 2021
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS AGENT
Reel/Frame 056285/0292 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 25, 2021
From: BAZARSKY, ALEXANDER; SHARON, ERAN; ALROD, IDAN
To: WESTERN DIGITAL TECHNOLOGIES, INC.
Reel/Frame 055712/0359 →
Continuity (2)
Provisional Application 63092731 · Oct 16, 2020
Related Publication 20220122674A1 · Apr 21, 2022