Distribution of logical-to-physical address entries across bank groups
A memory system may include a volatile memory that is configured to store an address data structure that includes a plurality of logical-to-physical address entries. The address data structure may be stored across a plurality of bank groups of the volatile memory. A controller may be configured to store consecutive logical-to-physical address entries across different bank groups. In turn, during read and write operations for data sets associated with consecutive logical addresses, read requests for physical addresses where the data sets are stored may be sent to multiple bank groups and processed by the multiple banks in parallel.
1. A storage system, comprising:
one or more memories comprising a first memory area and a second memory area different from the first memory area; and
one or more controllers configured to cause:
writing logical-to-physical address entries of an address data structure into the first and second memory areas;
randomly selecting a memory location to store a logical-to-physical address entry, wherein the randomly selected memory location is in the first memory area or the second memory area, and wherein the first memory area or the second memory area, where the randomly selected memory location resides, is different from a memory area in which a consecutive logical-to-physical address entry is stored; and
reading the logical-to-physical address entries to retrieve associated data,
wherein both of the first memory area and the second memory area are volatile memories,
wherein the one or more controllers are configured to cause:
determining that at least a first number or a first percentage of pairs of consecutive logical-to-physical address entries has a first logical-to-physical address entry stored in one of the first memory area or the second memory area and has a second logical-to-physical address entry stored in another one of the first memory area or the second memory area; and
after the determining, writing a first logical-to-physical address entry into a given memory area of the one or more memories without determining whether a consecutive logical-to-physical address entry is stored in the same given memory area, and
wherein the consecutive logical-to-physical address entries comprise at least two logical-to-physical address entries associated with at least two consecutive logical addresses.
2. The storage system of claim 1 , wherein writing the logical-to-physical address entries of the address data structure into the first and second memory areas comprises: writing non-consecutive logical-to-physical address entries of the address data structure into consecutively-addressed memory locations of the first memory area,
wherein the non-consecutive logical-to-physical address entries comprise at least two logical-to-physical address entries associated with at least two non-consecutive logical addresses.
3. The storage system of claim 1 , wherein the one or more memories comprise an N-number of memory areas, the N-number of memory areas including at least the first memory area and the second memory area, wherein each of the N-number of memory areas is accessible via a respective one of a plurality of interfaces, and wherein N is a positive integer.
4. The storage system of claim 3 , wherein each of the N-number of memory areas comprises a respective one of a plurality of bank groups, wherein each of the bank groups comprises an M-number of a plurality of banks, wherein each bank is configured to store a different set of every (N×M)th logical-to-physical address entries, and wherein M is a positive integer.
5. The storage system of claim 1 , wherein the one or more controllers are configured to cause storing no consecutive logical-to-physical address entries of the address data structure into the first memory area or the second memory area.
6. The storage system of claim 1 , wherein the one or more memories further comprise a third memory area comprising consecutively-addressed memory locations configured to store consecutive logical-to-physical address entries.
7. A method, comprising:
writing logical-to-physical address entries of an address data structure into a first memory area and a second memory area, wherein the second memory area is different from the first memory area;
randomly selecting a memory location to store a logical-to-physical address entry, wherein the randomly selected memory location is in the first memory area or the second memory area, and wherein the first memory area or the second memory area, where the randomly selected memory location resides, is different from a memory area in which a consecutive logical-to-physical address entry is stored; and
reading the logical-to-physical address entries to retrieve associated data,
wherein both of the first memory area and the second memory area are volatile memories,
wherein the method comprises:
determining that at least a first number or a first percentage of pairs of consecutive logical-to-physical address entries has a first logical-to-physical address entry stored in one of the first memory area or the second memory area and has a second logical-to-physical address entry stored in another one of the first memory area or the second memory area; and
after the determining, writing a first logical-to-physical address entry into a given memory area without determining whether a consecutive logical-to-physical address entry is stored in the same given memory area, and
wherein the consecutive logical-to-physical address entries comprise at least two logical-to-physical address entries associated with at least two consecutive logical addresses.
8. The method of claim 7 , wherein writing the logical-to-physical address entries of the address data structure into the first and second memory areas comprises: writing non-consecutive logical-to-physical address entries of the address data structure into consecutively-addressed memory locations of the first memory area,
wherein the non-consecutive logical-to-physical address entries comprise at least two logical-to-physical address entries associated with at least two non-consecutive logical addresses.
9. The method of claim 7 , wherein one or more memories comprise an N-number of memory areas, the N-number of memory areas including at least the first memory area and the second memory area, wherein each of the N-number of memory areas is accessible via a respective one of a plurality of interfaces, and wherein N is a positive integer.
10. The method of claim 9 , wherein each of the N-number of memory areas comprises a respective one of a plurality of bank groups, wherein each of the bank groups comprises an M-number of a plurality of banks, wherein each bank is configured to store a different set of every (N×M)th logical-to-physical address entries, and wherein M is a positive integer.
11. The method of claim 7 , wherein no consecutive logical-to-physical address entries of the address data structure are stored into the first memory area or the second memory area.
12. An apparatus, comprising:
means for writing logical-to-physical address entries of an address data structure into a first memory area and a second memory area, wherein the second memory area is different from the first memory area;
means for randomly selecting a memory location to store a logical-to-physical address entry, wherein the randomly selected memory location is in the first memory area or the second memory area, and wherein the first memory area or the second memory area, where the randomly selected memory location resides, is different from a memory area in which a consecutive logical-to-physical address entry is stored;
means for reading the logical-to-physical address entries to retrieve associated data;
means for determining that at least a first number or a first percentage of pairs of consecutive logical-to-physical address entries has a first logical-to-physical address entry stored in one of the first memory area or the second memory area and has a second logical-to-physical address entry stored in another one of the first memory area or the second memory area; and
means for writing a first logical-to-physical address entry into a given memory area of the one or more memories without determining whether a consecutive logical-to-physical address entry is stored in the same given memory area,
wherein both of the first memory area and the second memory area are volatile memories, and
wherein the consecutive logical-to-physical address entries comprise at least two logical-to-physical address entries associated with at least two consecutive logical addresses.
13. The apparatus of claim 12 , wherein the means for writing the logical-to-physical address entries of the address data structure into the first and second memory areas comprises: means for writing non-consecutive logical-to-physical address entries of the address data structure into consecutively-addressed memory locations of the first memory area,
wherein the non-consecutive logical-to-physical address entries comprise at least two logical-to-physical address entries associated with at least two non-consecutive logical addresses.