Method and system for improving word line data retention for memory blocks
Storage devices are capable of utilizing failed bit count (FBC) reduction devices to reduce FBCs for word lines in blocks. An FBC reduction device may include a FBC count component, a threshold component, a pre-verify component, and a soft program component. The FBC count component may access the FBC for the word line, where the block has unprogrammed word lines in an unprogrammed region separated from programmed word lines of a programmed region by the word line. The threshold component may determine whether the FBC of the word line exceeds a predetermined threshold. When the FBC exceeds the threshold, the pre-verify component may perform pre-verify operations on the programmed region. The soft program component may program the word line with first data equal to second data programmed in a second block. In response to disabling pre-verify operations, the program component may program the unprogrammed word lines in the unprogrammed region.
1. A method for managing a block in a storage device, comprising:
accessing a failed bit count (FBC) for a boundary word line in the block;
determining whether the FBC of the boundary word line exceeds a predetermined threshold;
in response to the FBC of the boundary word line exceeding the predetermined threshold, performing at least one pre-verify operation on one or more of the non-boundary word lines in the block;
programming the boundary word line; and
programming any remaining unprogrammed word lines within the block.
2. The method of claim 1 , wherein the block has one or more programmed word lines in a programmed region, and one or more unprogrammed word lines in an unprogrammed region.
3. The method of claim 2 , wherein the boundary word line separates the programmed word lines of the programmed region from the unprogrammed word lines of the unprogrammed region.
4. The method of claim 3 , wherein the method further includes programming the boundary word line with first data equal to second data that is programmed in a second block in the storage device.
5. The method of claim 4 , block wherein the second block comprises a source block, and wherein the source block comprises at least one or more of a source single-level cell (SLC) block, a multi-level cell (MLC) block, a triple-level cell (TLC) block, a quad-level cell (QLC) block, or a penta-level cell (PLC) block.
6. The method of claim 4 , wherein the second block is a block in which an error was previously detected.
7. The method of claim 3 , wherein the at least one pre-verify operation is performed on the programmed region of the block.
8. The method of claim 7 , wherein the method further includes, in response to programming the boundary word line, disabling the at least one pre-verify operation on the programmed region of the block.
9. The method of claim 1 , wherein the block is an open block.
10. The method of claim 1 , wherein the programmed first data of the word line is configured by a soft program component.
11. The method of claim 10 , wherein the soft program component comprises a soft-fine programming operation and a soft programming operation.
12. A storage device, comprising:
one or more memories; and
one or more controllers configured to:
access one or more failed bit counts (FBCs) for one or more pages of a boundary word line in a block;
determine whether any of the FBCs of any of the pages of the boundary word line exceed a predetermined threshold;
in response to at least one FBC of at least one page of the boundary word line exceeding the predetermined threshold, perform pre-verify operations on one or more of the programmed word lines in the programmed region;
programming the boundary word line; and
programming any remaining unprogrammed word lines within the block.
13. The storage device of claim 12 , wherein performing the pre-verify operations on one or more of the programmed word lines in the programmed region is done in response to all FBCs of all pages of the boundary word line exceeding the predetermined threshold.
14. The storage device of claim 12 , wherein the boundary word line is programmed with data copied from a source block.
15. The storage device of claim 14 , wherein the source block comprises at least one or more of a SLC block, a MLC block, a TLC block, a QLC block, a PLC block, and any block with a predetermined error.
16. The storage device of claim 14 , wherein the boundary word line programming is configured by a soft program component.
17. The storage device of claim 16 , wherein the soft program component comprises a soft-fine programming operation and a soft programming operation, and wherein the soft program component includes one or more tunable parameters that are configured to control both the soft and soft-fine programming operations.
18. The storage device of claim 17 , wherein tunable parameters include trim parameters.
19. The storage device of claim 12 , wherein the programming any remaining unprogrammed word lines within the block is done with a foggy-fine programming method.
20. A storage device, comprising:
a failed bit count (FBC) reduction device;
one or more memories communicatively coupled to the FBC reduction device; and
one or more controllers communicatively coupled to at least one or more of the memories and the FBC reduction device, wherein the FBC reduction device comprises:
an FBC count component configured to access a FBC for a word line in a block;
a threshold component configured to determine whether the FBC of the word line exceeds a predetermined threshold;
a pre-verify component configured to, in response to the FBC of the word line exceeding the predetermined threshold, perform pre-verify operations on one or more programmed word lines within the block;
a soft program component configured to program the word line with data equal to data received from a source block; and
a program component configured to program the unprogrammed word lines in the unprogrammed region of the block.