Expandable memory for use with solid state systems and devices
The present disclosure describes technologies and techniques for use by a data storage controller—such as a controller for use with a NAND or other non-volatile memory (NVM)—to provide a user-expandable memory space. In examples described herein, a customer may choose to purchase access to only a portion of the total available memory space of a consumer device, such as a smartphone. Later, the customer may expand the user-accessible memory space. In one example, the customer submits suitable payment via a communication network to a centralized authorization server, which returns an unlock key. Components within the data storage controller of the consumer device then use the key to unlock additional memory space within the device. In this manner, if the initial amount of memory the consumer paid for becomes full, the consumer may conveniently expand the amount of user-accessible memory.
1. A data storage device, comprising:
a non-volatile memory (NVM) device; and
a processing circuit configured to:
enable access to a first amount of memory within the NVM device while restricting access to a second amount of memory,
authorize access to the second amount of memory within the NVM device based on an indication of authorization received from a host device,
enable access to the second amount of memory in response to the indication of authorization, and
perform a program erase cycle (PEC) balancing operation on blocks within both the first and second amounts of memory in response to the indication of authorization.
2. The data storage device of claim 1 , wherein the processing circuit is further configured to apply wear leveling operations to a total physical memory of the NVM device even if only the first amount of memory is enabled for access.
3. The data storage device of claim 1 ,
wherein the indication of authorization includes an authorization key, and
wherein the processing circuit is further configured to verify authorization using a pre-stored comparison key.
4. The data storage device of claim 1 ,
wherein the processing circuit is further configured to restrict access to a preselected amount of memory within the NVM device, and
wherein the second amount of memory comprises at least a portion of the preselected amount of memory.
5. The data storage device of claim 1 ,
wherein the second amount of memory is larger than the first amount of memory, and
wherein the processing circuit is further configured to expand the amount of memory that a user can access from the first amount to the second amount.
6. The data storage device of claim 1 :
wherein the first amount of memory corresponds to a first logical partition of a physical memory of the NVM device, and
wherein the second amount of memory corresponds to a second logical partition of the physical memory of the NVM device.
7. The data storage device of claim 6 ,
wherein the physical memory further comprises a portion of reserved memory.
8. A method for use by a data storage device having a data storage controller and a non-volatile memory (NVM) device, the method comprising:
enabling access to a first amount of memory within a total amount of memory within the NVM device;
receiving an indication that access is permitted to a second amount of memory within the total amount of memory within the NVM device;
enabling access to the second amount of memory within the NVM device in response to the indication; and
perform a program erase cycle (PEC) balancing operation on blocks within both the first and second amounts of memory in response to the indication that access is permitted.
9. The method of claim 8 , wherein the second amount of memory is larger than the first amount of memory.
10. The method of claim 8 ,
wherein enabling access to the first amount of memory includes enabling access to a first logical partition of a physical memory of the NVM device, and
wherein enabling access to the second amount of memory includes enabling access to a second logical partition of the physical memory of the NVM device.
11. The method of claim 8 , further comprising performing wear leveling operations on a total amount of physical memory of the NVM device even if access is enabled only for the first amount of memory.
12. The method of claim 8 :
wherein enabling access to the first amount of memory includes providing a first logical block addresses (LBA) range corresponding to the first amount of memory, and
wherein enabling access to the second amount of memory includes expanding the LBA range to additionally include the second amount of memory.
13. The method of claim 8 :
wherein enabling access to the first amount of memory includes executing a partitioning request to enable a first partition within a memory space of the NVM device that corresponds to the first amount of memory, and
wherein enabling access to the second amount of memory includes executing a repartitioning request to the NVM device to repartition the memory space of the NVM device to include the first amount of memory and the second amount of memory.
14. The method of claim 8 :
wherein receiving the indication includes receiving an authorization key from an authorization server via a host device coupled to the data storage device, and
wherein enabling access to the second amount of memory includes confirming authorization using a pre-stored comparison key.
15. The method of claim 8 , wherein the NVM device comprises a NAND storage device, and wherein enabling access to a first and second amounts of memory includes enabling access to first and second NAND partitions, respectively.