Granted Patent B2

US 10,481,816 · App. 15/787,694 · Granted Nov 19, 2019

Abstract

Claims (100)

1. An apparatus, comprising:

a non-volatile memory die comprising a non-volatile memory medium;

a plurality of sets of data latches of the non-volatile memory die, the sets of data latches configured to facilitate transmission of data to and from the non-volatile memory medium, wherein each of the sets of data latches is associated with a different identifier; and

an on-die controller in communication with the sets of data latches, the on-die controller configured to:

receive a first command for a first memory operation, the first command comprising a selected identifier;

execute the first memory operation on the non-volatile memory medium using a set of latches of the plurality of sets of data latches, the set of data latches associated with the selected identifier;

receive a second command for a second memory operation while executing the first memory operation;

determine that the second memory operation uses fewer data latches than the first memory operation; and

in response to the determination:

pause execution of the first memory operation, and

perform the second memory operation using a subset of data latches of the set of data latches used to execute the first memory operation.

2. The apparatus of claim 1 , further comprising:

a memory controller in communication with the on-die controller, the memory controller configured to:

in response to receiving an input/output (I/O) command, selecting the non-volatile memory die for an I/O operation corresponding to the I/O command;

select an identifier of a plurality of identifiers to generate the selected identifier associated with the set of data latches; and

transmit the first command to the on-die controller.

3. The apparatus of claim 1 , wherein:

the set of latches comprises a first latch including an assigned first identifier and a second latch including an assigned second identifier; and

the on-die controller is further configured to execute the first memory operation utilizing the first latch with the assigned first identifier and the second latch with the assigned second identifier.

4. The apparatus of claim 3 , wherein the on-die controller is further configured to:

assign a third identifier to the first latch in response to receiving the second command; and

utilize the first latch with the third identifier to facilitate execution of the second memory operation.

5. The apparatus of claim 4 , wherein the third identifier comprises a prefix added to the assigned first identifier.

6. The apparatus of claim 5 , wherein, in response to receiving the second command prior to completing the first memory operation, the on-die controller is further configured to:

pause execution of the first memory operation;

execute the second memory operation using the first latch with the third identifier;

store data of the first memory operation in the second latch;

in response to completing the second memory operation, remove the prefix from the assigned first identifier to return the assigned first identifier to the first latch; and

resume executing the first memory operation using the first latch with the assigned first identifier and the second latch with the assigned second identifier.

7. The apparatus of claim 6 , wherein:

the first memory operation is a “program” operation; and

the second memory operation is one of a “read” operation, a “flush” operation, and an “erase” operation.

8. The apparatus of claim 1 , wherein:

the set of latches comprises a first latch and a second latch; and

the on-die controller is further configured to:

dynamically assign a first identifier of a plurality of identifiers to the first latch;

dynamically assign a second identifier of the plurality of identifiers to the second latch; and

execute the first memory operation utilizing the first latch with the dynamically assigned first identifier and the second latch with the dynamically assigned second identifier.

9. The apparatus of claim 8 , wherein:

the first latch executes the second memory operation; and

the on-die controller is further configured to:

assign a third identifier in the plurality of identifiers to the first latch in response to receiving the second command; and

utilize the first latch with the third identifier to facilitate execution of the second memory operation.

10. The apparatus of claim 9 , wherein the third identifier comprises one of:

the dynamically assigned first identifier and a prefix for the dynamically assigned first identifier; and

a new dynamically assigned identifier.

11. The apparatus of claim 8 , wherein in response to receiving the second command prior to completing the first memory operation, the on-die controller is further configured to:

execute the second memory operation using the first latch with the third identifier;

store data of the first memory operation in the second latch;

re-assign the dynamically assigned first identifier to the first latch in response to completing the second memory operation; and

resume executing the first memory operation using the first latch with the dynamically assigned first identifier and the second latch with the dynamically assigned second identifier; and

wherein the on-die controller re-assigns the dynamically assigned first identifier by one of:

removing a prefix from the dynamically assigned first identifier; and

replacing the third identifier with the dynamically assigned first identifier.

12. The apparatus of claim 8 , wherein:

the first memory operation is a “program” operation; and

the second memory operation is one of a “read” operation, a “flush” operation, and an “erase” operation.

13. The apparatus of claim 12 , wherein:

each latch is assigned a latch identifier; and

the on-die controller is further configured to dynamically modify the latch identifier in response to receiving a second command from the device controller.

14. The apparatus of claim 13 , wherein the on-die controller is further configured to dynamically modify the latch identifier by one of:

adding a prefix to the latch identifier; and

assigning a new latch identifier to a latch.

15. The apparatus of claim 14 , wherein:

the prefix is added to the identifier; and

the on-die controller is further configured to remove the latch identifier in response to completing a second memory operation associated with the second command.

16. The apparatus of claim 14 , wherein:

the new latch identifier is assigned to the latch; and

the on-die controller is further configured to replace the new latch identifier with a previous latch identifier for the latch.

17. A system, comprising:

a storage device comprising a device controller; and

a storage die in communication with the device controller, the storage die comprising:

a plurality of sets of data latches configured to facilitate transmission of data to and from the storage die,

wherein each of the sets of data latches is associated with a different identifier; and

an on-die controller in communication with the sets of data latches, the on-die controller configured to:

receive, from the device controller, a first command for a first memory operation, the first command comprising a selected identifier of a plurality of latch identifiers;

execute the first memory operation on the storage die using a set of data latches of the plurality of sets of data latches, the set of data latches associated with the selected identifier;

receive a second command for a second memory operation while executing the first memory operation;

determine that the second memory operation uses fewer data latches than the first memory operation; and

in response to the determination:

pause execution of the first memory operation, and

perform the second memory operation using a subset of data latches of the set of data latches used to execute the first memory operation,

wherein the subset of data latches is associated with a different selected identifier than the selected identifier for the set of data latches.

18. The system of claim 17 , wherein the device controller is configured to:

in response to receiving an input/output (I/O) command, select the storage die for an I/O operation corresponding to the I/O command;

select an identifier of a plurality of identifiers to generate the selected identifier associated with the set of data latches; and

transmit the command to the on-die controller.

19. An apparatus, comprising:

means for associating each of a plurality of sets of data latches of a memory die with a different identifier;

means for receiving, from a device controller, a first command for a first memory operation on the memory die, the first command comprising a selected identifier of the different latch identifiers;

means for executing the first memory operation on the memory die using a set of data latches of the plurality of sets of data latches on the memory die, the set of data latches associated with the selected identifier;

means for receiving a second command for a second memory operation while executing the first memory operation;

means for determining that the second memory operation uses fewer data latches than the first memory operation;

means for pausing execution of the first memory operation in response to the determination; and

means for performing the second memory operation using a subset of data latches of the set of data latches used to execute the first memory operation,

wherein the subset of data latches is associated with a different selected identifier than the selected identifier for the set of data latches.

20. The apparatus of claim 19 , further comprising:

means for, in response to receiving an input/output (I/O) command, selecting the memory die for an I/O operation corresponding to the I/O command;

means for selecting an identifier of a plurality of identifiers to generate, the selected identifier associated with the set of data latches; and

means for transmitting the command to the memory die.

Assignments (10)