Dynamic multi-stage decoding
Methods and systems for decoding raw data may include determining a sequence of a plurality of read-level voltages based on previous decoding data and executing a multi-stage decoding operation to decode raw data read from the plurality of memory cells using the determined sequence of the plurality of read-level voltages. Decoded data is returned from the multi-stage decoding operation upon completion of the multi-stage decoding operation and the previous decoding data is updated based on results of the multi-stage decoding operation.
1. A data storage system, comprising:
memory comprising memory cells; and
one or more controllers configured to cause:
determining a sequence of read-level voltages based on decoding data, wherein the decoding data indicates which one or more read-level voltages have been used for one or more decoding operations;
executing a multi-stage decoding operation to decode raw data read from the memory cells;
providing decoded data from the multi-stage decoding operation upon completion of the multi-stage decoding operation; and
updating a decoding data indication,
wherein:
the multi-stage decoding operation comprises one or more hard decoding operations and one or more soft decoding operations;
the one or more hard decoding operations are configured to use the determined sequence of read-level voltages for decoding;
the one or more soft decoding operations are configured to use a second sequence of read-level voltages for decoding; and
the second sequence of read-level voltages is different from the determined sequence of read-level voltages.
2. The data storage system of claim 1 , wherein:
a first counter corresponds to a first group of read-level voltages, and the first counter has a first value;
a second counter corresponds to a second group of read-level voltages, and the second counter has a second value; and
the determining comprises determining the sequence of read-level voltages based on switching between the first group and the second group.
3. The data storage system of claim 2 , wherein the switching is based on the first value and the second value.
4. The data storage system of claim 2 , wherein the read-level voltages of the first group are different from the read-level voltages of the second group.
5. The data storage system of claim 1 , wherein the one or more controllers are configured to cause:
each unsuccessful hard decoding operation of the multi-stage decoding operation to be followed by up to multiple soft decoding operations regardless of availability of another hard decoding operation; and
executing two or more consecutive soft decoding operations without re-reading the memory cells.
6. The data storage system of claim 1 , wherein:
after an unsuccessful first hard decoding operation on a first data using a first read-level voltage and after an unsuccessful second hard decoding operation on the first data using a second read-level voltage, when a read-level voltage of a third hard decoding operation of a particular stage of the multi-stage decoding operation is same as the first read-level voltage of the unsuccessful first hard decoding operation, the one or more controllers are configured to skip the third hard decoding operation on the first data and configured to execute one or more soft decoding operations of the particular stage.
7. The data storage system of claim 1 , wherein each stage of the multi-stage decoding operation is associated with one respective read-level voltage from another sequence.
8. The data storage system of claim 1 , wherein:
the decoding data indication comprises counter values of respective counters corresponding to the read-level voltages; and
determining the sequence of read-level voltages comprises ordering the read-level voltages according to the counter values of the respective counters.
9. The data storage system of claim 1 , wherein:
updating the decoding data indication comprises incrementing a counter value corresponding to a read-level voltage of the read-level voltages used to obtain successfully decoded data; and
the one or more controllers are configured to cause determining the sequence of read-level voltages based on the counter value.
10. A method for a data storage system, the method comprising:
determining a sequence of read-level voltages based on decoding data, wherein the decoding data indicates which one or more read-level voltages have been used for one or more decoding operations;
executing a multi-stage decoding operation to decode raw data read from memory cells;
providing decoded data from the multi-stage decoding operation upon completion of the multi-stage decoding operation; and
updating a decoding data indication,
wherein:
the multi-stage decoding operation comprises one or more hard decoding operations and one or more soft decoding operations;
the one or more hard decoding operations are configured to use the determined sequence of read-level voltages for decoding;
the one or more soft decoding operations are configured to use a second sequence of read-level voltages for decoding; and
the second sequence of read-level voltages is different from the determined sequence of read-level voltages.
11. The method of claim 10 , wherein:
a first counter corresponds to a first group of read-level voltages, and the first counter has a first value;
a second counter corresponds to a second group of read-level voltages, and the second counter has a second value; and
the determining comprises determining the sequence of read-level voltages based on switching between the first group and the second group.
12. The method of claim 11 , wherein the switching is based on the first value and the second value.
13. The method of claim 11 , wherein the read-level voltages of the first group are different from the read-level voltages of the second group.
14. The method of claim 10 , wherein:
each unsuccessful hard decoding operation of the multi-stage decoding operation is followed by up to multiple soft decoding operations regardless of availability of another hard decoding operation; and
two or more consecutive soft decoding operations are executed without re-reading the memory cells.
15. The method of claim 10 , wherein:
after an unsuccessful first hard decoding operation on a first data using a first read-level voltage and after an unsuccessful second hard decoding operation on the first data using a second read-level voltage, when a read-level voltage of a third hard decoding operation of a particular stage of the multi-stage decoding operation is same as the first read-level voltage of the unsuccessful first hard decoding operation, the third hard decoding operation on the first data is skipped, and one or more soft decoding operations of the particular stage are executed.
16. The method of claim 10 , wherein each stage of the multi-stage decoding operation is associated with one respective read-level voltage from another sequence.
17. The method of claim 10 , wherein:
the decoding data indication comprises counter values of respective counters corresponding to the read-level voltages; and
determining the sequence of read-level voltages comprises ordering the read-level voltages according to the counter values of the respective counters.
18. An apparatus, comprising:
means for determining a sequence of read-level voltages based on decoding data, wherein the decoding data indicates which one or more read-level voltages have been used for one or more decoding operations;
means for executing a multi-stage decoding operation to decode raw data read from memory cells;
means for providing decoded data from the multi-stage decoding operation upon completion of the multi-stage decoding operation; and
means for updating a decoding data indication,
wherein:
the multi-stage decoding operation comprises one or more hard decoding operations and one or more soft decoding operations;
the one or more hard decoding operations are configured to use the determined sequence of read-level voltages for decoding;
the one or more soft decoding operations are configured to use a second sequence of read-level voltages for decoding; and
the second sequence of read-level voltages is different from the determined sequence of read-level voltages.
19. The apparatus of claim 18 , wherein:
a first counter corresponds to a first group of read-level voltages, and the first counter has a first value;
a second counter corresponds to a second group of read-level voltages, and the second counter has a second value; and
the means for determining comprises means for determining the sequence of read-level voltages based on switching between the first group and the second group.
20. The apparatus of claim 19 , wherein the switching is based on the first value and the second value.