IP Library Granted Patent US 12,506,015
Granted Patent B2
US 12,506,015 · App. 17/841,357 · Granted Dec 23, 2025

Semiconductor wafer thinned by horizontal stealth lasing

Inventors: Yi Wu (Shanghai, CN); Junrong Yan (Shanghai, CN); Zhonghua Qian (Shanghai, CN); Keming Zhou (Shanghai, CN); Kailei Zhang (Shanghai, CN)
Assignee: Sandisk Technologies, Inc.
H01L21/463H01L21/68764
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Quick Facts
Patent No.
US 12,506,015
App. No.
17/841,357
Granted
Dec 23, 2025
Kind
B2
Abstract

A method includes the step of thinning a semiconductor wafer by a horizontal stealth lasing process, and semiconductor wafers, dies and devices formed thereby. After formation of an integrated circuit layer on a semiconductor wafer, the wafer may be thinned by supporting an active surface of the wafer on a rotating chuck, and focusing a horizontally-oriented laser in multiple cycles at different radii within the rotating wafer. Upon completion of the multiple cycles, a portion of the wafer substrate may be removed, leaving the wafer thinned to its final thickness. Thereafter, a vertical stealth lasing process may be performed to cut individual semicondcutor dies from the thinned wafer.

Claims (22)

1. A method of separating a semiconductor die from a wafer comprising a plurality of semiconductor dies, the wafer comprising a first major planar surface, a second major planar surface and an outer edge extending between the first and second major planar surfaces, wherein each die comprises a plurality of integrated circuits formed in the first major planar surface of the wafer, the method comprising:

rotating the wafer;

penetrating the outer edge of the wafer with a laser beam without removing portions of the outer edge;

pulsing the laser at distinct points at a given radial distance from a center of the wafer;

repeating said step of pulsing the laser at distinct points at multiple other radial distances from the center of the wafer;

thinning the wafer by allowing cracks to propagate between the distinct points at multiple radii; and

dicing the semiconductor die from the thinned wafer.

2. The method of claim 1 , wherein the wafer is supported on a chuck with the first major planar surface facing the chuck for said step of thinning the wafer.

3. The method of claim 2 , wherein said chuck rotates during said step of thinning the wafer.

4. The method of claim 2 , wherein a focal point of the laser is adjusted to different radial positions of the wafer as the wafer is rotating on the chuck to generate pinpoint holes at the different radial positions in a plane parallel to the first major surface.

5. The method of claim 1 , wherein the step of thinning the wafer by application of one or more laser beams through the outer edge of the wafer comprises the step of generating pinpoint holes from a pair of laser assemblies in a plane parallel to the first major planar surface of the wafer.

6. The method of claim 1 , wherein the step of dicing the semiconductor die from the thinned wafer comprises the step of generating pinpoint holes in a plane orthogonal to the first major planar surface of the wafer, cracks propagating between the pinpoint holes to dice the die from the wafer.

7. A method of separating a semiconductor die from a wafer comprising a plurality of semiconductor dies, the wafer comprising a first major planar surface, a second major planar surface and an outer edge extending between the first and second major planar surfaces, wherein each die comprises a plurality of integrated circuits formed in the first major planar surface of the wafer, the method comprising:

rotating the wafer;

pulsing a laser beam through the outer edge of the wafer as the wafer rotates to form focal points within an interior of the wafer, each focal point creating a localized pinpoint hole around a circle;

changing one of a distance of the focal point from a laser beam generator, or a position of the laser beam generator from the wafer, to create multiple circles of localized pinpoint holes at different radii;

thinning the wafer by allowing cracks to propagate between the localized pinpoint holes at different radii; and

dicing the semiconductor die from the thinned wafer.

8. The method of claim 7 , wherein the wafer is supported on a chuck with the first major planar surface facing the chuck for said step of thinning the wafer.

9. The method of claim 8 , wherein said chuck rotates during said step of thinning the wafer.

10. The method of claim 7 , wherein the step of thinning the wafer by application of one or more laser beams through the outer edge of the wafer comprises the step of generating pinpoint holes from a pair of laser assemblies in a plane parallel to the first major planar surface of the wafer.

11. The method of claim 1 , wherein the step of dicing the semiconductor die from the thinned wafer comprises the step of generating pinpoint holes in a plane orthogonal to the first major planar surface of the wafer, cracks propagating between the pinpoint holes to dice the die from the wafer.

Assignments (8)
PARTIAL RELEASE OF SECURITY INTERESTS Recorded Apr 25, 2025
From: JPMORGAN CHASE BANK, N.A., AS AGENT
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 071382/0001 →
SECURITY AGREEMENT Recorded Apr 25, 2025
From: SANDISK TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 071050/0001 →
PATENT COLLATERAL AGREEMENT Recorded Aug 23, 2024
From: SANDISK TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS THE AGENT
Reel/Frame 068762/0494 →
CHANGE OF NAME Recorded Jun 27, 2024
From: SANDISK TECHNOLOGIES, INC.
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 067982/0032 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 29, 2024
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 067567/0682 →
PATENT COLLATERAL AGREEMENT - DDTL LOAN AGREEMENT Recorded Aug 21, 2023
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A.
Reel/Frame 067045/0156 →
PATENT COLLATERAL AGREEMENT - A&R LOAN AGREEMENT Recorded Aug 21, 2023
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A.
Reel/Frame 064715/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 15, 2022
From: WU, YI; YAN, JUNRONG; QIAN, ZHONGHUA; ZHOU, KEMING; ZHANG, KAILEI
To: WESTERN DIGITAL TECHNOLOGIES, INC.
Reel/Frame 060214/0982 →
Continuity (1)
Related Publication 20230411169A1 · Dec 21, 2023
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