Quality of service based arbitrations optimized for enterprise solid state drives
A method and apparatus for operating a solid state drive is disclosed comprising receiving at least two commands from a host requiring an action by the solid state drive in a preliminary order, ordering the at least two commands based upon a quality of service classification for the at least two commands to a final order and executing the at least two commands on the solid state drive in the final order, wherein an operational parameter of the solid state drive is modified by at least one of the at least two commands.
1. A memory device, comprising:
at least one memory array configured to store data provided to the array; and
a controller coupled to the at least one memory array, wherein the controller is configured to:
receive at least two commands from a host requiring an action by the memory device in a preliminary order;
order the at least two commands based upon a quality of service classification for the at least two commands to a final order, wherein the ordering the at least two commands comprises:
estimating a time of completion for each of the at least two commands based on the preliminary order of completion for each of the at least two commands and a time stamp indicating a time of arrival for each of the at least two commands at the memory device; and
comparing the estimated time of completion for each of the at least two commands to a threshold; and
reordering the preliminary order of completion to the final order of completion if the estimated time of completion for each of the at least two commands exceeds the threshold such that each of the at least two commands are completed by the threshold in the final order of completion; and
execute the at least two commands on the memory device in the final order, wherein an operational parameter of the memory device is modified by at least one of the at least two commands.
2. The memory device of claim 1 , wherein the controller is further configured to transmit the at least two commands from the host to the memory device.
3. The memory device claim 1 , wherein the controller is further configured to transmit a completion notification for each of the at least two commands from the memory device to the host that each of the at least two commands have been completed.
4. The memory device of claim 3 , wherein the controller is further configured to send an interrupt notification to the host from the memory device upon sending the completion notification.
5. The memory device of claim 1 , wherein the controller is further configured to attach the time stamp indicating the time of arrival for each of the at least two commands at the memory device prior to ordering the at least two commands.
6. The memory device of claim 1 , wherein the ordering of the at least two commands accounts for the time of arrival for each of the commands.
7. The memory device of claim 1 , wherein the reordering the preliminary order of completion accounts for a bit error rate.
8. The memory device of claim 1 , wherein the reordering the preliminary order of completion accounts for die utilization.
9. The memory device of claim 1 , wherein the reordering the preliminary order of completion accounts for a type of memory zone in which data is stored.
10. The memory device claim 1 , wherein the reordering the preliminary order of completion involves a command arbitration performed by a controller of the memory device.
11. The memory device of claim 10 , wherein the command arbitration is performed in a weighted round robin algorithm.
12. The memory device claim 11 , wherein weights used for the weighted round robin algorithm are assigned to the at least two commands by the host.
13. The memory device claim 12 , wherein the weights used are an administrative category, an urgent category, a high priority category, a medium priority category and a low priority category.