IP Library › Granted Patent US 12,399,813
Granted Patent B2
US 12,399,813 · App. 18/510,857 · Granted Aug 26, 2025

Sense time separation in foggy-fine program to improve optimal VT width

Inventors: Xiaoyu Che (San Jose, CA); Guirong Liang (Cupertino, CA)
Assignee: Sandisk Technologies, Inc.
G06F12/023
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Quick Facts
Patent No.
US 12,399,813
App. No.
18/510,857
Granted
Aug 26, 2025
Kind
B2
Abstract

A memory device includes a plurality of memory cells and control circuitry configured to perform a foggy-fine programming operation in which memory cells are programmed in multiple programming passes. To perform the foggy-fine programming operation, the control circuity is configured to perform a first pass of the foggy-fine programming operation on the memory cells, perform, in accordance with a first sense time, a first sensing operation on the memory cells programmed in the first pass of the foggy-fine programming operation, perform a second pass of the foggy-fine programming operation on the memory cells previously programmed in the first pass of the foggy-fine programming operation, and perform, in accordance with a second sense time, a second sensing operation on the memory cells programmed in the first pass and the second pass of the foggy-fine programming operation, wherein the second sense time is different from the first sense time.

Claims (37)

1. A memory device, comprising:

a plurality of memory cells; and

control circuitry configured to perform a foggy-fine programming operation in which memory cells are programmed in multiple programming passes, wherein, to perform the foggy-fine programming operation, the control circuity is configured to

perform a first pass of the foggy-fine programming operation on the memory cells,

perform, in accordance with a first sense time, a first sensing operation on the memory cells programmed in the first pass of the foggy-fine programming operation,

perform a second pass of the foggy-fine programming operation on the memory cells previously programmed in the first pass of the foggy-fine programming operation, and

perform, in accordance with a second sense time, a second sensing operation on the memory cells programmed in the first pass and the second pass of the foggy-fine programming operation, wherein the second sense time is different from the first sense time.

2. The memory device of claim 1 , wherein the second sense time is longer than the first sense time.

3. The memory device of claim 1 , wherein performing the first sensing operation includes using the first sense time in a very low sense period of the first sensing operation and using a third sense time greater than the first sense time in a very high sense period of the first sensing operation.

4. The memory device of claim 3 , wherein performing the second sensing operation includes using the second sense time in a very low sense period of the second sensing operation and using a fourth sense time greater than the second sense time in a very high sense period of the second sensing operation.

5. The memory device of claim 4 , wherein each of the first, second, third, and fourth sense times are different.

6. The memory device of claim 1 , wherein the first sense time is a sum of the second sense time and a negative offset value.

7. The memory device of claim 1 , wherein the foggy-fine programming operation is a quad level cell (QLC) programming operation.

8. The memory device of claim 7 , wherein sense times used for different programmed states of the memory cells are different.

9. A method for operating a memory device including a plurality of memory cells, the method comprising:

performing a foggy-fine programming operation in which memory cells are programmed in multiple programming passes, wherein performing the foggy-fine programming operation includes

performing a first pass of the foggy-fine programming operation on the memory cells,

performing, in accordance with a first sense time, a first sensing operation on the memory cells programmed in the first pass of the foggy-fine programming operation,

performing a second pass of the foggy-fine programming operation on the memory cells previously programmed in the first pass of the foggy-fine programming operation, and

performing, in accordance with a second sense time, a second sensing operation on the memory cells programmed in the first pass and the second pass of the foggy-fine programming operation, wherein the second sense time is different from the first sense time.

10. The method of claim 9 , wherein the second sense time is longer than the first sense time.

11. The method of claim 9 , wherein performing the first sensing operation includes using the first sense time in a very low sense period of the first sensing operation and using a third sense time greater than the first sense time in a very high sense period of the first sensing operation.

12. The method of claim 11 , wherein performing the second sensing operation includes using the second sense time in a very low sense period of the second sensing operation and using a fourth sense time greater than the second sense time in a very high sense period of the second sensing operation.

13. The method of claim 12 , wherein each of the first, second, third, and fourth sense times are different.

14. The method of claim 9 , wherein the first sense time is a sum of the second sense time and a negative offset value.

15. The method of claim 9 , wherein the foggy-fine programming operation is a quad level cell (QLC) programming operation.

16. The method of claim 15 , wherein sense times used for different programmed states of the memory cells are different.

17. A memory device, comprising:

a plurality of memory cells; and

control means for performing a foggy-fine programming operation in which memory cells are programmed in multiple programming passes, wherein, to perform the foggy-fine programming operation, the control means

performs a first pass of the foggy-fine programming operation on the memory cells,

performs, in accordance with a first sense time, a first sensing operation on the memory cells programmed in the first pass of the foggy-fine programming operation,

performs a second pass of the foggy-fine programming operation on the memory cells previously programmed in the first pass of the foggy-fine programming operation, and

performs, in accordance with a second sense time, a second sensing operation on the memory cells programmed in the first pass and the second pass of the foggy-fine programming operation, wherein the second sense time is different from the first sense time.

18. The memory device of claim 17 , wherein the second sense time is longer than the first sense time.

19. The memory device of claim 17 , wherein performing the first sensing operation includes using the first sense time in a very low sense period of the first sensing operation and using a third sense time greater than the first sense time in a very high sense period of the first sensing operation, and wherein performing the second sensing operation includes using the second sense time in a very low sense period of the second sensing operation and using a fourth sense time greater than the second sense time in a very high sense period of the second sensing operation.

20. The memory device of claim 19 , wherein each of the first, second, third, and fourth sense times are different.

Assignments (8)
PARTIAL RELEASE OF SECURITY INTERESTS Recorded Apr 25, 2025
From: JPMORGAN CHASE BANK, N.A., AS AGENT
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 071382/0001 →
SECURITY AGREEMENT Recorded Apr 25, 2025
From: SANDISK TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 071050/0001 →
PATENT COLLATERAL AGREEMENT Recorded Aug 23, 2024
From: SANDISK TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS THE AGENT
Reel/Frame 068762/0494 →
CHANGE OF NAME Recorded Jun 27, 2024
From: SANDISK TECHNOLOGIES, INC.
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 067982/0032 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 29, 2024
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 067567/0682 →
PATENT COLLATERAL AGREEMENT (AR) Recorded Feb 22, 2024
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS THE AGENT
Reel/Frame 066648/0284 →
PATENT COLLATERAL AGREEMENT (DDTL) Recorded Feb 22, 2024
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS THE AGENT
Reel/Frame 066648/0206 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 12, 2024
From: CHE, XIAOYU; LIANG, GUIRONG
To: WESTERN DIGITAL TECHNOLOGIES, INC.
Reel/Frame 066109/0903 →
Continuity (1)
Related Publication 20250165385A1 · May 22, 2025
References Cited (8)
US 8908441B1 · Dutta et al. · 2014 [cited by applicant]
US 9478293B2 · Yanagida et al. · 2016 [cited by applicant]
US 10394649B2 · Alrod et al. · 2019 [cited by applicant]
US 11139031B1 · Chen et al. · 2021 [cited by applicant]
US 11532370B1 · Yang et al. · 2022 [cited by applicant]
US 20240161831A1 · Jung · 2024 [cited by examiner]
US 20240212767A1 · Prakash · 2024 [cited by examiner]
US 20240304249A1 · Choi · 2024 [cited by examiner]