Memory device and operating method thereof
A memory device may include memory cells connected to a selected word line, and a peripheral circuit configured to store information regarding a foggy program pass loop in which a target program state is determined as foggy program pass during a foggy program operation on the selected word line, calculate a fine program pass loop based on the foggy program pass loop, and determine the target program state as fine program pass in the fine program pass loop of a fine program operation on the selected word line.
1 . A memory device comprising:
memory cells connected to a selected word line; and
a peripheral circuit configured to:
store, as a foggy program pass loop for a target program state, information regarding an Xth foggy program loop in which the target program state is determined as foggy program pass during a foggy program operation including one or more foggy program loops for the selected word line;
before performing a fine program operation including one or more fine program loops for the selected word line, determine, according to a predetermined relationship based on the foggy program pass loop, a Yth fine program loop as a fine program pass loop for the target program state; and
determine the target program state as a fine program pass in the fine program pass loop during the fine program operation, regardless of states of the memory cells.
2 . The memory device according to claim 1 , wherein the peripheral circuit determines the fine program pass loop based on at least one of the foggy program pass loop, a predetermined first foggy program voltage, a first fine program voltage, an increase amount of a fine program voltage, a foggy verification voltage and a fine verification voltage of the target program state, and Incremental Step Pulse Program (ISPP) efficiency.
3 . The memory device according to claim 1 , wherein the peripheral circuit applies a fine program voltage and a fine verification voltage to the selected word line in the fine program pass loop and then determines the target program state as the fine program pass regardless of whether the target program state is determined as the fine program pass or a fine program fail resulting from application of the fine verification voltage.
4 . The memory device according to claim 1 , wherein the peripheral circuit applies a fine program voltage in the fine program pass loop and then determines the target program state as the fine program pass without applying a fine verification voltage to the selected word line to verify the target program state.
5 . The memory device according to claim 1 , wherein a first fine program voltage of the fine program operation is higher than a first foggy program voltage of the foggy program operation.
6 . The memory device according to claim 1 , wherein before applying a first fine program voltage to the selected word line during the fine program operation, the peripheral circuit performs an operation that pre-applies a first fine verification voltage to verify a first program state and determines a memory cell in the first program state as a program inhibited memory cell based on a result of the operation that pre-applies the first fine verification voltage.
7 . A memory device comprising:
memory cells connected to a selected word line; and
a peripheral circuit configured to:
store, as a foggy program pass loop for a target program state, information regarding an Xth foggy program loop in which the target program state is determined as foggy program pass during a foggy program operation including one or more foggy program loops for the selected word line;
before performing a fine program operation including one or more fine program loops for the selected word line, determine a fine program pass voltage for the target program state according to a predetermined relationship based on the foggy program pass loop; and
determine the target program state as a fine program pass after applying the fine program pass voltage to the selected word line during the fine program operation, regardless of states of the memory cells.
8 . The memory device according to claim 7 , wherein the peripheral circuit determines the fine program pass voltage based on at least one of the foggy program pass loop, a predetermined first foggy program voltage, an increase amount of a foggy program voltage, a foggy verification voltage and a fine verification voltage of the target program state, and Incremental Step Pulse Program (ISPP) efficiency.
9 . The memory device according to claim 7 , the peripheral circuit applies the fine program pass voltage and a fine verification voltage to the selected word line, and then determines the target program state as the fine program pass regardless of whether the target program state is determined as the fine program pass or a fine program fail resulting from application of the fine verification voltage.
10 . The memory device according to claim 7 , wherein the peripheral circuit applies the fine program pass voltage, and then determines the target program state as the fine program pass without applying a fine verification voltage to the selected word line to verify the target program state.
11 . The memory device according to claim 7 , wherein a first fine program voltage of the fine program operation is higher than a first foggy program voltage of the foggy program operation.
12 . The memory device according to claim 7 , wherein before applying a first fine program voltage to the selected word line during the fine program operation, the peripheral circuit performs an operation that pre-applies a first fine verification voltage to verify a first program state and determines a memory cell in the first program state as a program inhibited memory cell based on a result of the operation that pre-applies the first fine verification voltage.
13 . A method of operating a memory device, the method comprising:
storing, as a foggy program pass loop for a target program state, information regarding an Xth foggy program loop in which the target program state is determined as foggy program pass during a foggy program operation including one or more foggy program loops for a selected word line connected to memory cells;
determining a fine program pass condition for the target program state according to a predetermined relationship based on the foggy program pass loop before performing a fine program operation including one or more fine program loops for the selected word line; and
determining the target program state as a fine program pass when the fine program pass condition is satisfied during a fine program operation, regardless of states of the memory cells.
14 . The method according to claim 13 , wherein the fine program pass condition comprises performing a Yth fine program loop during the fine program operation.
15 . The method according to claim 14 , wherein determining the fine program pass condition comprises determining the Yth fine program loop based on at least one of the foggy program pass loop, a predetermined first foggy program voltage, a first fine program voltage, an increase amount of a fine program voltage, a foggy verification voltage and a fine verification voltage of the target program state, and Incremental Step Pulse Program (ISPP) efficiency.
16 . The method according to claim 13 , wherein the fine program pass condition comprises applying a fine program pass voltage to the selected word line during the fine program operation.
17 . The method according to claim 16 , wherein determining the fine program pass condition comprises determining the fine program pass voltage based on at least one of the foggy program pass loop, a predetermined first foggy program voltage, an increase amount of a foggy program voltage, a foggy verification voltage and a fine verification voltage of the target program state, and Incremental Step Pulse Program (ISPP) efficiency.