Semiconductor memory device and data write method thereof

1. A semiconductor memory device comprising:

a memory cell array including a plurality of memory cells which are arranged in a matrix at intersections between a plurality of word lines and a plurality of bit lines;

a word line driving circuit which applies a voltage to the word lines;

a bit line control circuit including a buffer which retains a verify result of the memory cell array, and a bit scan circuit which counts a verify pass bit number on the basis of the verify result that is retained in the buffer; and

a control circuit which controls the word line driving circuit and the bit line control circuit, the control circuit executing control to perform a verify operation with respect to only a lowest threshold voltage level of the memory cell at a time of a data write operation, and to skip the verify operation with respect to the other threshold voltage levels.

2. The device according to claim 1 , wherein the control circuit determines, at the time of the data write operation, whether the verify pass bit number of the lowest threshold voltage level, which is counted by the bit scan circuit, is a prescribed bit number or more, and

the control circuit further executes control, if the verify pass bit number is the prescribed bit number or more, to perform the verify operation with respect to only the lowest threshold voltage level and a threshold voltage level that is higher than the lowest threshold voltage level, and to skip the verify operation with respect to the other threshold voltage levels.

3. The device according to claim 2 , wherein the control circuit further executes control to skip a subsequent verify operation of a threshold voltage level at which data write is finished.

4. The device according to claim 1 , further comprising a memory which is electrically connected to the buffer and stores write/read data which is input from outside.

5. The device according to claim 1 , further comprising a column decoder which is electrically connected to the bit line control circuit and selects data in a column direction.

6. The device according to claim 1 , wherein the memory cell has a multi-layer structure including a tunnel insulation film, a charge accumulation layer, an inter-gate insulation film and a control electrode layer, which are successively provided on a semiconductor substrate.

7. A semiconductor memory device comprising:

a memory cell array including a plurality of memory cells which are arranged in a matrix at intersections between a plurality of word lines and a plurality of bit lines, and are capable of storing multi-bit data;

a word line driving circuit which applies a voltage to the word lines;

a bit line control circuit including a buffer which retains a verify result of the memory cell array, and a bit scan circuit which counts a verify pass bit number on the basis of the verify result that is retained in the buffer; and

a control circuit which controls the word line driving circuit and the bit line control circuit, the control circuit executing control to perform a verify operation with respect to only a first threshold voltage level which is higher than a lowest threshold voltage level of the memory cell at a time of a data write operation, and to skip the verify operation with respect to the other threshold voltage levels.

8. The device according to claim 7 , wherein the control circuit determines, at the time of the data write operation, whether the verify pass bit number of the first threshold voltage level, which is counted by the bit scan circuit, is a prescribed bit number or more, and

the control circuit further executes control, if the verify pass bit number is the prescribed bit number or more, to perform the verify operation with respect to the first threshold voltage level and a second threshold voltage level that is higher than the first threshold voltage level, and to skip the verify operation with respect to the other threshold voltage levels.

9. The device according to claim 8 , wherein at the time of the data write operation, the control circuit completes the verify operation of a highest threshold voltage level after finishing the verify operation of the second threshold voltage level, and then performs the verify operation with respect to only the lowest threshold voltage level and skips the verify operation with respect to the other threshold voltage levels,

the control circuit determines whether the verify pass bit number of the lowest threshold voltage level, which is counted by the bit scan circuit, is a prescribed bit number or more, and

the control circuit further executes control, if the verify pass bit number is the prescribed bit number or more, to perform the verify operation with respect to only the lowest threshold voltage level and a threshold voltage level that is higher than the lowest threshold voltage level, and to skip the verify operation with respect to the other threshold voltage levels.

10. The device according to claim 9 , wherein the control circuit further executes control to skip a subsequent verify operation of a threshold voltage level at which data write is finished.

11. The device according to claim 7 , further comprising a memory which is electrically connected to the buffer and stores write/read data which is input from outside.

12. The device according to claim 7 , further comprising a column decoder which is electrically connected to the bit line control circuit and selects data in a column direction.

13. The device according to claim 7 , wherein the memory cell has a multi-layer structure including a tunnel insulation film, a charge accumulation layer, an inter-gate insulation film and a control electrode layer, which are successively provided on a semiconductor substrate.

14. A data write method of a semiconductor memory device, comprising:

executing a verify operation with respect to only a lowest threshold voltage level of a memory cell, and skipping the verify operation with respect to the other threshold voltage levels;

counting a verify pass bit number of the lowest threshold voltage level;

determining whether the counted verify pass bit number of the lowest threshold voltage level is a prescribed bit number or more; and

executing, if the verify pass bit number is the prescribed bit number or more, the verify operation with respect to only the lowest threshold voltage level and a threshold voltage level that is higher than the lowest threshold voltage level, and skipping the verify operation with respect to the other threshold voltage levels.

15. The method according to claim 14 , further comprising executing the verify operation with respect to only the lowest threshold voltage level of the memory cell, and applying a write pulse on the basis of write data which is input from outside, prior to skipping the verify operation with respect to the other threshold voltage levels.

16. The method according to claim 14 , further comprising skipping a subsequent verify operation of a threshold voltage level at which data write is finished.

17. The method according to claim 14 , wherein the device comprises:

a memory cell array including a plurality of memory cells which are arranged in a matrix at intersections between a plurality of word lines and a plurality of bit lines;

a word line driving circuit which applies a voltage to the word lines;

a bit line control circuit including a buffer which retains a verify result of the memory cell array, and a bit scan circuit which counts a verify pass bit number on the basis of the verify result that is retained in the buffer; and

a control circuit which controls the word line driving circuit and the bit line control circuit.

18. The method according to claim 17 , wherein the device further comprises a memory which is electrically connected to the buffer and stores write/read data which is input from outside.

19. The method according to claim 17 , wherein the device further comprises a column decoder which is electrically connected to the bit line control circuit and selects data in a column direction.

20. The method according to claim 17 , wherein the memory cell has a multi-layer structure including a tunnel insulation film, a charge accumulation layer, an inter-gate insulation film and a control electrode layer, which are successively provided on a semiconductor substrate.