Command sequence for hybrid erase mode for high data retention in memory device
View Patent ↗Apparatuses and techniques are described for performing an erase operation for a set of memory cells, where the erase operation includes an all word line erase phase to save time followed by an odd-even word line erase phase to improve data retention. A transition to the odd-even word line erase phase can be triggered when the memory cells pass a first verify test which indicates that the threshold voltages of the memory cells have decreased below a first voltage. Or, the transition can be triggered when a threshold number of erase-verify iterations have been performed. The erase operation may be completed when the memory cells pass a second verify test which indicates that the threshold voltages of the memory cells have decreased below a second voltage which is less than the first voltage.
1. An apparatus, comprising:
a control circuit configured to perform a hybrid erase operation for a block of memory cells, the memory cells are connected to a plurality of word lines, the hybrid erase operation comprises an all word line erase of the block followed by an odd-even word line erase of the block, and the control circuit, to perform the hybrid erase operation, is configured to:
issue a prefix command; and
issue an erase command after the prefix command, wherein:
the hybrid erase operation comprises the all word line erase of the block until a first verify test is passed by the block, after which the hybrid erase operation comprises the odd-even word line erase of the block;
the hybrid erase operation is completed when a second verify test is passed by the block; and
a verify voltage of the second verify test is lower than a verify voltage of the first verify test.
2. The apparatus of claim 1 , wherein:
the control circuit is configured to issue the prefix command in a first command cycle and to issue the erase command in a second command cycle; and
the prefix command indicates that the second command cycle follows the first command cycle.
3. The apparatus of claim 1 , wherein:
the prefix command comprises an erase block command and an address of the block.
4. The apparatus of claim 1 , wherein:
the erase command comprises a status return command; and
the control circuit is configured to determine a pass/fail result of a verify test in the hybrid erase operation based on the status return command.
5. The apparatus of claim 1 , wherein:
the all word line erase of the block comprises a concurrent erase of memory cells connected to each of the plurality of word lines; and
the odd-even word line erase of the block comprises an erase of memory cells connected to odd-numbered word lines of the plurality of word lines separate from an erase of memory cells connected to even-numbered word lines of the plurality of word lines.
6. An apparatus, comprising:
a control circuit configured to perform a hybrid erase operation for a block of memory cells, the memory cells are connected to a plurality of word lines, the hybrid erase operation comprises an all word line erase of the block followed by an odd-even word line erase of the block, and the control circuit, to perform the hybrid erase operation, is configured to:
issue a dedicated command for the hybrid erase operation, wherein:
the hybrid erase operation comprises the all word line erase of the block until a first verify test is passed by the block, after which the hybrid erase operation comprises the odd-even word line erase of the block; and
the hybrid erase operation is completed when a second verify test is passed by the block; and
a verify voltage of the second verify test is lower than a verify voltage of the first verify test.
7. The apparatus of claim 6 , wherein:
the dedicated command comprises an erase block command, an address of the block and a status return command.
8. The apparatus of claim 7 , wherein:
the dedicated command comprises a status return command; and
the control circuit is configured to determine a pass/fail result of the hybrid erase operation based on the status return command.
9. The apparatus of claim 6 , wherein:
the control circuit is on one die and the block of memory cells is on another die.
10. The apparatus of claim 6 , wherein:
the all word line erase of the block comprises a concurrent erase of memory cells connected to each of the plurality of word lines; and
the odd-even word line erase of the block comprises an erase of memory cells connected to odd-numbered word lines of the plurality of word lines separate from an erase of memory cells connected to even-numbered word lines of the plurality of word lines.
11. A method, comprising:
issuing a command to perform an all word line erase for a plurality of memory cells in which memory cells connected to a plurality of word lines are concurrently erased until the plurality of memory cells pass a first verify test;
issuing a status command to determine that the plurality of memory cells pass the first verify test; and
in response to the determining that the plurality of memory cells pass the first verify test, issuing a command to perform an odd-even word line erase for the plurality of memory cells in which memory cells connected to odd-numbered word lines of the plurality of word lines are erased separately from memory cells connected to even-numbered word lines of the plurality of word lines until the plurality of memory cells pass a second verify test, wherein:
the first verify test is configured to test threshold voltages of the plurality of memory cells relative to a first voltage; and
the second verify test is configured to test threshold voltages of the plurality of memory cells relative to a second voltage which is lower than the first voltage.
12. The method of claim 11 , further comprising issuing a command to:
perform the first verify test concurrently for the memory cells connected to each of the plurality of word lines during the all word line erase; and
perform the second verify test for memory cells connected to the odd-numbered word lines separately from memory cells connected to the even-numbered word lines during the odd-even word line erase.
13. The method of claim 12 , further comprising issuing a command to:
inhibit the memory cells connected to the odd-numbered word lines from further erase when the memory cells connected to the odd-numbered word lines pass the second verify test in an erase-verify iteration which is different than an erase-verify iteration in which the memory cells connected to the even-numbered word lines pass the second verify test.