Distributed grouped terminations for multiple memory integrated circuit systems
The present disclosure generally relates to apparatuses and methods for transmission line termination. In one embodiment an apparatus includes a stack of uniform memory dies and a storage controller. Each uniform memory die in the stack of uniform memory dies couples to a transmission line in series through wire bonds to form a transmission path. Each memory die includes an on-die termination resistance circuit connected to the transmission line. The on-die termination resistance circuit provides a minimum termination resistance. The storage controller addresses a target uniform memory die of the stack of uniform memory dies for an operation. The storage controller enables the on-die termination resistance circuits of a plurality of uniform memory dies along the transmission path. The storage controller transmits a data signal for the operation to the target uniform memory die with the on-die termination resistance circuit enabled for the plurality of uniform memory dies.
1. An apparatus, comprising:
a stack of uniform memory dies coupled to a transmission line by a set of wire bonds that connect each uniform memory die of the stack of uniform memory dies in series to form a transmission path;
each memory die of the stack of uniform memory dies comprising:
an on-die termination resistance circuit connected to the transmission line, the on-die termination resistance circuit configured to provide a minimum termination resistance; and
a storage controller configured to:
address a target uniform memory die of the stack of uniform memory dies for an operation;
enable the on-die termination resistance circuits of a plurality of uniform memory dies along the transmission path; and
transmit a data signal for the operation to the target uniform memory die with the on-die termination resistance circuit enabled for the plurality of uniform memory dies.
2. The apparatus of claim 1 , wherein the storage controller is configured to transmit the data signal at a frequency greater than 1600 Hz and wherein the plurality of uniform memory dies comprises four uniform memory dies.
3. The apparatus of claim 1 , wherein the stack of uniform memory dies comprises more than four uniform memory die and wherein the plurality of uniform memory dies comprises more than two uniform memory dies.
4. The apparatus of claim 1 , wherein the on-die termination resistance circuit comprises a passive resistance circuit.
5. The apparatus of claim 1 , wherein the on-die termination resistance circuit comprises an active resistance circuit.
6. The apparatus of claim 1 , wherein the on-die termination resistance circuit comprises a programmable resistance circuit.
7. The apparatus of claim 6 , wherein the programmable resistance circuit comprises a parallel circuit of a set of resistors and a set of switches configured to be activated by a die controller of the plurality of uniform memory dies based on a programmable resistance setting stored in a register of the die controller.
8. The apparatus of claim 1 , wherein the minimum termination resistance is configured such that a parasitic capacitance contributed by each of the uniform memory dies in the stack of uniform memory dies is reduced by 25%.
9. The apparatus of claim 1 , wherein the minimum termination resistance comprises a termination resistance of at least 100 ohms.
10. The apparatus of claim 1 , wherein the minimum termination resistance comprises a termination resistance of no less than 200 ohms.
11. The apparatus of claim 1 , wherein the plurality of uniform memory dies are positioned adjacent to each other at an end of the transmission path.
12. The apparatus of claim 1 , wherein enabling the on-die termination resistance circuits of the plurality of uniform memory dies creates an effective termination resistance for the transmission path that is less than the minimum termination resistance of anyone of the uniform memory dies individually of the stack of uniform memory dies.
13. The apparatus of claim 1 , wherein the transmission line comprises a single-ended transmission line.
14. The apparatus of claim 1 , wherein the transmission line comprises a differential transmission line.
15. An apparatus, comprising:
a stack of uniform memory dies coupled to a transmission line by a set of wire bonds that connect each uniform memory die of the stack of uniform memory dies in series to form a transmission path;
each uniform memory die of the stack of uniform memory dies comprising:
an on-die termination resistance circuit configured to connect to the transmission line when a uniform memory die is powered on, the on-die termination resistance circuit comprising a programmable resistance circuit configured to provide a termination resistance during transmission of a data signal to a target uniform memory die; and
a storage controller configured to:
send a storage command to a target uniform memory die of the stack of uniform memory dies for an operation;
direct at least four uniform memory die along the transmission path to provide termination resistance during a portion of the operation, the at least four uniform memory die different from the target uniform memory die; and
transmit a plurality of data signals for the operation to the target uniform memory die with the at least four uniform memory die generating an effective termination resistance for the transmission path during the operation.
16. The apparatus of claim 15 , wherein the stack of uniform memory dies comprises eight uniform memory die and the at least four uniform memory die programmed to provide 200 ohms of termination resistance which is greater than a minimum termination resistance that is 100 ohms.
17. The apparatus of claim 15 , wherein the at least four uniform memory die directed to provide termination resistance during the operation provide a distributed termination resistance that substantially matches a characteristic impedance of the transmission line and wherein the programmable resistance circuit is configured to provide a range of termination resistance between the minimum termination resistance and a maximum termination resistance.
18. A method, comprising:
sending a storage command to a target uniform memory die of a stack of uniform memory dies for an operation, the stack of uniform memory dies connected in series to a transmission line by wire bonds to form a transmission path;
activating an on-die termination resistance circuit of at least four adjacent uniform memory die along the transmission path to provide an effective termination resistance lower than a minimum termination resistance of each of the on-die termination resistance circuits individually, the at least four uniform memory die different from the target uniform memory die; and
transmitting data signals for the operation to the target uniform memory die with the at least four uniform memory die providing parallel termination resistance during the operation.
19. The method of claim 18 , wherein the at least four adjacent uniform memory die comprise the last uniform memory die along the transmission path.
20. The method of claim 18 , wherein the on-die termination resistance circuit comprises at least one electronic component comprising hardware configured to provide the minimum termination resistance to the transmission path during operations when the uniform memory die is powered off and is connected to the transmission line.