Adaptive error correction codes for data storage systems
View Patent ↗A data storage system configured to adaptively code data is disclosed. In one embodiment, a data storage system controller determines a common memory page size, such as an E-page size, for a non-volatile memory array. Based on the common memory page size, the controller selects a low-density parity-check (LDPC) code word length from a plurality of pre-defined LDPC code word lengths. The controller determines LDPC coding parameters for coding data written to or read from the memory array based on the selected LDPC code word length. By using the plurality of pre-defined LDPC code word lengths, the data storage system can support multiple non-volatile memory page formats, including memory page formats in which the common memory page size does not equal any LDPC code word length of the plurality of pre-defined LDPC code word lengths. Flexibility and efficiency of data coding can thereby be achieved.
1. A solid-state storage system, comprising:
a non-volatile memory array comprising a plurality of memory pages, each memory page having a common memory page size; and
a controller configured to:
determine the common memory page size for the non-volatile memory array;
select a low-density parity-check (LDPC) code word length from a plurality of pre-defined LDPC code word lengths, the LDPC code word length having a size equal to or greater than the common memory page size for the non-volatile memory array; and
determine LDPC coding parameters for coding data written to or read from one or more memory pages of the non-volatile memory array based at least in part on the LDPC code word length,
wherein the controller is configured to support multiple non-volatile memory page sizes using the plurality of pre-defined LDPC code word lengths and to support a memory page size in which the common memory page size does not equal any LDPC code word length of the plurality of pre-defined LDPC code word lengths.
2. The solid-state storage system of claim 1 , wherein the LDPC coding parameters comprise a P matrix size, a column weight, and a row weight, and further comprise at least one of a code rate, an amount of user data, and an amount of parity data.
3. The solid-state storage system of claim 1 , wherein the controller is configured to select the LDPC code word length having a minimum size equal to or greater than the common memory page size for the non-volatile memory array.
4. The solid-state storage system of claim 1 , wherein the memory pages comprise error-correcting code pages (E-pages).
5. The solid-state storage system of claim 1 , wherein the controller is further configured to:
determine parity data for padded user data using the LDPC coding parameters, the padded user data comprising user data and padding data; and
store the user data and the parity data in a memory page of the non-volatile memory array.
6. The solid-state storage system of claim 5 , wherein an amount of the padding data of the padded user data depends at least in part on a difference between the LDPC code word length and the common memory page size for the non-volatile memory array.
7. In a data storage system comprising a controller, a method of coding data, the method comprising:
determining a common memory page size for a non-volatile memory array, the non-volatile memory array comprising a plurality of memory pages, each memory page having the common memory page size;
selecting a low-density parity-check (LDPC) code word length from a plurality of pre-defined LDPC code word lengths, the LDPC code word length having a size equal to or greater than the common memory page size for the non-volatile memory array; and
determining LDPC coding parameters for coding data written to or read from one or more memory pages of the non-volatile memory array based at least in part on the LDPC code word length,
whereby the method enables supporting of coding for multiple non-volatile memory page sizes using the plurality of pre-defined code word lengths and supporting of coding for a memory page size in which the common memory page size does not equal any LDPC code word length of the plurality of pre-defined LDPC code word lengths.
8. The method of claim 7 , wherein the LDPC coding parameters comprise a P matrix size, a column weight, and a row weight, and further comprise at least one of a code rate, an amount of user data, and an amount of parity data.
9. The method of claim 7 , wherein said selecting the LDPC code word length comprises selecting the LDPC code word length having a minimum size equal to or greater than the common memory page size for the non-volatile memory array.
10. The method of claim 7 , wherein the memory pages comprise error-correcting code pages (E-pages).
11. The method of claim 7 , further comprising:
determining parity data for padded user data using the LDPC coding parameters, the padded user data comprising user data and padding data; and
storing the user data and the parity data in a memory page of the non-volatile memory array.
12. The method of claim 11 , wherein an amount of the padding data of the padded user data depends at least in part on a difference between the LDPC code word length and the common memory page size for the non-volatile memory array.
13. A solid-state storage system, comprising:
a non-volatile memory array comprising a plurality of memory pages, each memory page having a common memory page size; and
a controller configured to:
determine the common memory page size for the non-volatile memory array;
select a code word length from a plurality of pre-defined code word lengths, the code word length having a size equal to or greater than the common memory page size for the non-volatile memory array; and
determine coding parameters for coding data written to or read from one or more memory pages of the non-volatile memory array based at least in part on the code word length,
wherein the controller is configured to support multiple non-volatile memory page sizes using the plurality of pre-defined code word lengths and to support a memory page size in which the common memory page size does not equal any code word length of the plurality of pre-defined code word lengths.
14. The solid-state storage system of claim 13 , wherein the coding parameters comprise low-density parity-check (LDPC) coding parameters including a P matrix size, a column weight, and a row weight, and further including at least one of a code rate, an amount of user data, and an amount of parity data.
15. The solid-state storage system of claim 13 , wherein the controller is configured to select the code word length having a minimum size equal to or greater than the common memory page size for the non-volatile memory array.
16. The solid-state storage system of claim 13 , wherein the memory pages comprise error-correcting code pages (E-pages).
17. The solid-state storage system of claim 13 , wherein the controller is further configured to:
determine parity data for padded user data using the coding parameters, the padded user data comprising user data and padding data; and
store the user data and the parity data in a memory page of the non-volatile memory array.
18. The solid-state storage system of claim 17 , wherein an amount of the padding data of the padded user data depends at least in part on a difference between the code word length and the common memory page size for the non-volatile memory array.