IP Library Granted Patent US 10,445,242
Granted Patent B2
US 10,445,242 · App. 15/357,155 · Granted Oct 15, 2019

Invalidation data area for cache

Inventor: Pulkit Misra (Belmont, MA)
Assignee: Western Digital Technologies, Inc.
G06F12/0891G06F11/1471G06F12/0815G06F12/0866G06F12/121G06F2212/1024G06F2212/1041G06F2212/60G06F2212/62
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Quick Facts
Patent No.
US 10,445,242
App. No.
15/357,155
Granted
Oct 15, 2019
Kind
B2
Abstract

The present disclosure relates to caches, methods, and systems for using an invalidation data area. The cache can include a journal configured for tracking data blocks, and an invalidation data area configured for tracking invalidated data blocks associated with the data blocks tracked in the journal. The invalidation data area can be on a separate cache region from the journal. A method for invalidating a cache block can include determining a journal block tracking a memory address associated with a received write operation. The method can also include determining a mapped journal block based on the journal block and on an invalidation record. The method can also include determining whether write operations are outstanding. If so, the method can include aggregating the outstanding write operations and performing a single write operation based on the aggregated write operations.

Claims (36)

1. A method for invalidating a block in a cache, the method comprising:

determining a first journal block that is tracking a memory address associated with a received write operation, wherein the first journal block is stored in a journal of the cache, wherein the cache comprises a content locality cache, and wherein the journal tracks at least one of associated data blocks and independent data blocks in the content locality cache;

determining a second journal block based on the determined first journal block and based further on an invalidation record, wherein the second journal block and the invalidation record are stored in an invalidation data area of the cache;

determining whether further write operations are outstanding after the received write operation;

when further write operations are outstanding,

aggregating the outstanding further write operations with the received write operation and performing a single write operation based on the aggregated write operations; and

when no further write operations are outstanding,

performing the received write operation.

2. The method of claim 1 , wherein determining the second journal block comprises determining a mapped journal block number for the second journal block by:

determining an invalidation record number by dividing a journal block number associated with the first journal block by a capacity of the invalidation record in the invalidation data area and computing a ceiling function of the result of the division, wherein the invalidation record number identifies the invalidation record; and

determining the mapped journal block number by computing a modulo operation of the journal block number with the capacity of the invalidation record.

3. The method of claim 1 , wherein determining whether further write operations are outstanding comprises retrieving a field from an in-RAM data structure corresponding to the invalidation record.

4. The method of claim 1 , wherein aggregating the outstanding further write operations with the received write operation comprises:

queuing subsequent write operations;

identifying write operations that operate on the same data block; and

determining the single write operation based on the write operations that operate on the same data block.

5. The method of claim 1 , wherein the invalidation data area is on a separate region of the cache from the journal.

6. A system for invalidating a block in a cache, the system comprising:

a cache comprising a journal and an invalidation data area, wherein the cache comprises a content locality cache, and wherein the journal is configured to track at least one of associated data blocks and independent data blocks in the content locality cache; and

a means for:

determining a first journal block that is tracking a memory address associated with a received write operation, wherein the first journal block is stored in the journal of the cache;

determining a second journal block based on the determined first journal block and based further on an invalidation record, wherein the second journal block and the invalidation record are stored in the invalidation data area of the cache;

determining whether further write operations are outstanding after the received write operation;

when further write operations are outstanding,

aggregating the outstanding further write operations with the received write operation and performing a single write operation based on the aggregated write operations; and

when no further write operations are outstanding,

performing the received write operation.

7. The system of claim 6 , wherein determining the second journal block comprises determining a mapped journal block number for the second journal block by:

determining an invalidation record number by dividing a journal block number associated with the determined first journal block by a capacity of the invalidation record in the invalidation data area and computing a ceiling function of the result of the division, wherein the invalidation record number identifies the invalidation record; and

determining the mapped journal block number by computing a modulo operation of the journal block number with the capacity of the invalidation record.

8. The system of claim 6 , wherein determining whether further write operations are outstanding comprises retrieving a field from an in-RAM data structure corresponding to the invalidation record.

9. The system of claim 6 , wherein aggregating the outstanding further write operations with the received write operation comprises:

queuing subsequent write operations;

identifying write operations that operate on the same data block; and

determining the single write operation based on the write operations that operate on the same data block.

10. The system of claim 6 , wherein the invalidation data area is on a separate region of the cache from the journal.

Assignments (11)
SECURITY AGREEMENT (SUPPLEMENTAL) Recorded Nov 14, 2024
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 069411/0208 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 11, 2024
From: SANDISK TECHNOLOGIES, INC.
To: WESTERN DIGITAL TECHNOLOGIES, INC.
Reel/Frame 069168/0273 →
PATENT COLLATERAL AGREEMENT Recorded Aug 23, 2024
From: SANDISK TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS THE AGENT
Reel/Frame 068762/0494 →
CHANGE OF NAME Recorded Jun 27, 2024
From: SANDISK TECHNOLOGIES, INC.
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 067982/0032 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 29, 2024
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 067567/0682 →
PATENT COLLATERAL AGREEMENT - A&R LOAN AGREEMENT Recorded Aug 21, 2023
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A.
Reel/Frame 064715/0001 →
PATENT COLLATERAL AGREEMENT - DDTL LOAN AGREEMENT Recorded Aug 21, 2023
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A.
Reel/Frame 067045/0156 →
RELEASE OF SECURITY INTEREST AT REEL 052915 FRAME 0566 Recorded Feb 8, 2022
From: JPMORGAN CHASE BANK, N.A.
To: WESTERN DIGITAL TECHNOLOGIES, INC.
Reel/Frame 059127/0001 →
SECURITY INTEREST Recorded Feb 6, 2020
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS AGENT
Reel/Frame 052915/0566 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 2, 2019
From: HGST NETHERLANDS B.V.
To: WESTERN DIGITAL TECHNOLOGIES, INC.
Reel/Frame 049671/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 2, 2016
From: MISRA, PULKIT
To: HGST NETHERLANDS B.V.
Reel/Frame 040495/0978 →
Continuity (2)
Division 14316256 · Jun 26, 2014
Related Publication 20170068623A1 · Mar 9, 2017