Granted Patent B2

US 11,205,206 · App. 16/827,597 · Granted Dec 21, 2021

Inventors: Jaimeson Saley (Rochester, MN); Ali Khalili (Bryon, MN); Nicholas Waara (Rochester, MN); Alexis Dani (Comstock Park, MI)

Assignee: Western Digital Technologies, Inc.

G06Q30/04G06F3/0604G06F3/067G06F3/0653G06F3/0688

Abstract

Claims (70)

1. A system, comprising:

memories arranged in a plurality of circuit dies, the memories comprising a number of memory blocks; and

one or more processors configured to cause:

converting one or more logical memory addresses to one or more physical memory addresses associated with one or more memory blocks of the memory blocks, to write data to the one or more memory blocks;

identifying one or more circuit dies of the plurality of circuit dies associated with the one or more memory blocks;

executing one or more write operations to write the data to the one or more memory blocks that are within the one or more circuit dies of the plurality of circuit dies, based on the one or more physical memory addresses associated with the one or more memory blocks;

determining a number of write operations that have been performed on the memories arranged in the plurality of circuit dies, wherein the number of write operations reduces a lifetime of the memories after being performed on the memories; and

providing the number of write operations that have been performed on the memories arranged in the plurality of circuit dies, to enable tracking a percentage of the lifetime of the memories consumed by a quantity of write operations performed on the memories arranged in the plurality of circuit dies and to enable determining an amount of a fee associated with the provided number of write operations that have been performed on the memories arranged in the plurality of circuit dies,

wherein the system is configured to perform operations comprising:

determining the lifetime of the memories arranged in the plurality of circuit dies, based on the number of the memory blocks and a maximum number of write operations per memory block of the memory blocks; and

providing the amount of the fee associated with the provided number of write operations that have been performed on the memories arranged in the plurality of circuit dies.

2. The system of claim 1 , wherein the system is configured to perform operations comprising:

predicting a first number of write operations, before writing the data to the one or more memory blocks that are within the one or more circuit dies of the plurality of circuit dies based on the one or more physical memory addresses associated with the one or more memory blocks.

3. The system of claim 1 , wherein the system is configured to perform operations comprising:

predicting a second number of write operations before writing any data to the memories arranged in the plurality of circuit dies for an entity.

4. The system of claim 1 , wherein the determining the amount of the fee comprises:

determining the lifetime of the memories measured in units of an amount of write operations;

determining a value of a utilization factor by dividing the amount of write operations by the lifetime; and

using the value of the utilization factor to determine the amount of the fee.

5. The system of claim 4 , wherein the determining the amount of the fee comprises: using a tiered pricing schedule comprising different amounts of fees for different values of the utilization factor, and

wherein the amount of the fee for a second value of the utilization factor is greater than the amount of the fee for a first value of the utilization factor that is smaller than the second value.

6. The system of claim 1 , wherein the system comprises a counter, and wherein determining the number of write operations comprises determining the number of write operations using the counter.

7. The system of claim 1 , wherein the system is configured to perform operations comprising:

determining a second number of second write operations for writing data to the memories arranged in the plurality of circuit dies, the second number of second write operations associated with a first entity; and

determining a cumulative value of a workload related to the first entity for the memories over the lifetime of the memories, the cumulative value of the workload based at least in part on the number of write operations and the second number of second write operations.

8. A method, comprising:

converting one or more logical memory addresses to one or more physical memory addresses associated with one or more memory blocks, to write data to the one or more memory blocks, wherein memories are arranged in a plurality of circuit dies, the memories comprising a number of memory blocks, the memory blocks comprising the one or more memory blocks;

identifying one or more circuit dies of the plurality of circuit dies associated with the one or more memory blocks;

executing one or more write operations to write the data to the one or more memory blocks that are within the one or more circuit dies of the plurality of circuit dies, based on the one or more physical memory addresses associated with the one or more memory blocks;

determining a number of write operations that have been performed on the memories arranged in the plurality of circuit dies, wherein the number of write operations reduces a lifetime of the memories after being performed on the memories;

determining the lifetime of the memories arranged in the plurality of circuit dies, based on the number of the memory blocks and a maximum number of write operations per memory block of the memory blocks;

providing the number of write operations that have been performed on the memories arranged in the plurality of circuit dies, to enable tracking a percentage of the lifetime of the memories consumed by a quantity of write operations performed on the memories arranged in the plurality of circuit dies and to enable determining an amount of a fee associated with the provided number of write operations that have been performed on the memories arranged in the plurality of circuit dies; and

performing an operation to provide the amount of the fee associated with the provided number of write operations that have been performed on the memories arranged in the plurality of circuit dies.

9. The method of claim 8 , comprising:

predicting a first number of write operations, before writing the data to the one or more memory blocks that are within the one or more circuit dies of the plurality of circuit dies based on the one or more physical memory addresses associated with the one or more memory blocks.

10. The method of claim 8 , comprising:

predicting a second number of write operations before writing any data to the memories arranged in the plurality of circuit dies for an entity.

11. The method of claim 8 , wherein the determining the amount of the fee comprises:

determining the lifetime of the memories measured in units of an amount of write operations;

determining a value of a utilization factor by dividing the amount of write operations by the lifetime; and

using the value of the utilization factor to determine the amount of the fee.

12. The method of claim 11 , wherein the determining the amount of the fee comprises:

using a tiered pricing schedule comprising different amounts of fees for different values of the utilization factor, and

wherein the amount of the fee for a second value of the utilization factor is greater than the amount of the fee for a first value of the utilization factor that is smaller than the second value.

13. The method of claim 8 , comprising:

determining a second number of second write operations for writing data to the memories arranged in the plurality of circuit dies, the second number of second write operations associated with a first entity; and

determining a cumulative value of a workload related to the first entity for the memories over the lifetime of the memories, the cumulative value of the workload based at least in part on the number of write operations and the second number of second write operations.

14. An apparatus, comprising:

means for converting one or more logical memory addresses to one or more physical memory addresses associated with one or more memory blocks, to write data to the one or more memory blocks, wherein memories are arranged in a plurality of circuit dies, the memories comprising a number of memory blocks, the memory blocks comprising the one or more memory blocks;

means for identifying one or more circuit dies of the plurality of circuit dies associated with the one or more memory blocks;

means for executing one or more write operations to write the data to the one or more memory blocks that are within the one or more circuit dies of the plurality of circuit dies, based on the one or more physical memory addresses associated with the one or more memory blocks;

means for determining a number of write operations that have been performed on the memories arranged in the plurality of circuit dies, wherein the number of write operations reduces a lifetime of the memories after being performed on the memories;

means for determining the lifetime of the memories arranged in the plurality of circuit dies, based on the number of the memory blocks and a maximum number of write operations per memory block of the memory blocks;

means for providing the number of write operations that have been performed on the memories arranged in the plurality of circuit dies, to enable tracking a percentage of the lifetime of the memories consumed by a quantity of write operations performed on the memories arranged in the plurality of circuit dies and to enable determining an amount of a fee associated with the provided number of write operations that have been performed on the memories arranged in the plurality of circuit dies; and

means for performing an operation to provide the amount of the fee associated with the provided number of write operations that have been performed on the memories arranged in the plurality of circuit dies.

15. The apparatus of claim 14 , comprising:

means for predicting a first number of write operations, before writing the data to the one or more memory blocks that are within the one or more circuit dies of the plurality of circuit dies based on the one or more physical memory addresses associated with the one or more memory blocks.

16. The apparatus of claim 14 , comprising:

means for predicting a second number of write operations before writing any data to the memories arranged in the plurality of circuit dies for an entity.

17. The apparatus of claim 14 , wherein the means for determining the amount of the fee comprises:

means for determining the lifetime of the memories measured in units of an amount of write operations;

means for determining a value of a utilization factor by dividing the amount of write operations by the lifetime; and

means for using the value of the utilization factor to determine the amount of the fee.

18. The apparatus of claim 17 , wherein the means for determining the amount of the fee comprises:

means for using a tiered pricing schedule comprising different amounts of fees for different values of the utilization factor, and

wherein the amount of the fee for a second value of the utilization factor is greater than the amount of the fee for a first value of the utilization factor that is smaller than the second value.

19. The apparatus of claim 14 , wherein the apparatus comprises a counter, and wherein the means for determining the number of write operations comprises means for determining the number of write operations using the counter.

20. The apparatus of claim 14 , comprising:

means for determining a second number of second write operations for writing data to the memories arranged in the plurality of circuit dies, the second number of second write operations associated with a first entity; and

means for determining a cumulative value of a workload related to the first entity for the memories over the lifetime of the memories, the cumulative value of the workload based at least in part on the number of write operations and the second number of second write operations.

Assignments (11)

Continuity (2)