Partial reset of memory controller
Technology is described herein that provides a partial reset of a non-volatile memory controller. In one aspect, a non-volatile memory controller persists memory addresses of I/O queues across a partial reset of the non-volatile memory controller. The non-volatile memory controller may also persist a mapping between each I/O submission queue and a corresponding I/O completion queue across the partial reset. Persisting the addresses of the I/O queues and/or mappings alleviates the need for a host system and non-volatile memory controller to perform a lengthy process of sharing the addresses of the I/O queues and/or mappings.
1. An apparatus comprising:
a memory structure having non-volatile memory cells; and
a non-volatile memory controller in communication with the memory structure and configured to:
receive, from a host, memory addresses of I/O (Input/Output) submission queues and memory addresses of I/O completion queues;
receive, from the host, a mapping between each I/O submission queue of the I/O submission queues and a corresponding I/O completion queue of the I/O completion queues;
reset, in response to a partial reset of the non-volatile memory controller:
i) head pointers and tail pointers of the I/O submission queues; and
ii) head pointers and tail pointers of the I/O completion queues; and
persist the following across the partial reset of the non-volatile memory controller:
i) the memory addresses of the I/O submission queues;
ii) the memory addresses of the I/O completion queues; and
iii) the mapping between each I/O submission queue of the I/O submission queues and the corresponding I/O completion queue of the I/O completion queues.
2. The apparatus of claim 1 , further comprising the host, wherein the host is configured to:
trigger the partial reset of the non-volatile memory controller; and
clear content of the I/O submission queues and content of the I/O completion queues as a part of the partial reset of the non-volatile memory controller.
3. The apparatus of claim 2 , wherein the host is further configured to:
after the partial reset, preserve the mapping between each I/O submission queue of the I/O submission queues and the corresponding I/O completion queue of the I/O completion queues; and
after the content of the I/O submission queues and the content of the I/O completion queues has been cleared, place I/O commands on the I/O submission queues.
4. The apparatus of claim 1 , further comprising the host, wherein the host is configured to:
write to a register in the non-volatile memory controller to trigger the partial reset of the non-volatile memory controller.
5. The apparatus of claim 1 , further comprising the host, wherein the host is configured to:
provide the non-volatile memory controller with a vendor-specific command to trigger the partial reset of the non-volatile memory controller.
6. The apparatus of claim 1 , further comprising the host, wherein the host is configured to:
prior to the partial reset of the non-volatile memory controller, allocate host memory for the I/O submission queues and the I/O completion queues; and
after the partial reset of the non-volatile memory controller, preserve the allocation of the host memory for the I/O submission queues and the I/O completion queues.
7. The apparatus of claim 1 , further comprising the host, wherein the host is configured to:
prior to the partial reset of the non-volatile memory controller, allocate memory in the non-volatile memory controller for the I/O submission queues and the I/O completion queues; and
after the partial reset of the non-volatile memory controller, preserve the allocation of the memory in the non-volatile memory controller for the I/O submission queues and the I/O completion queues.
8. The apparatus of claim 1 , wherein the non-volatile memory controller is further configured to:
preserve an interrupt coalescing feature after the partial reset of the non-volatile memory controller.
9. The apparatus of claim 1 , wherein the non-volatile memory controller is further configured to:
prior to the partial reset, access the I/O submission queues and the I/O completion queues to process I/O commands from the host to access the non-volatile memory cells; and
after the partial reset, access the I/O submission queues and the I/O completion queues to process I/O commands from the host to access the non-volatile memory cells based on:
i) the persisted memory addresses of the I/O completion queues;
ii) the persisted memory addresses of the I/O submission queues; and
iii) the persisted mapping between each I/O submission queue of the I/O submission queues and the corresponding I/O completion queue of the I/O completion queues.
10. A method of operating a non-volatile storage device, the method comprising:
during an initialization of a non-volatile memory controller of the non-volatile storage device:
receiving memory addresses of I/O (Input/Output) submission queues and memory addresses of I/O completion queues; and
receiving a mapping between each I/O submission queue of the I/O submission queues and a corresponding I/O completion queue of the I/O completion queues;
accessing the I/O submission queues and the I/O completion queues to process I/O commands to access non-volatile memory in the non-volatile storage device;
in response to a partial reset of the non-volatile memory controller, clearing head pointers and tail pointers of the I/O submission queues and head pointers and tail pointers of the I/O completion queues; and
after the partial reset:
preserving the memory addresses of the I/O completion queues;
preserving the memory addresses of the I/O submission queues;
preserving the mapping between each I/O submission queue of the I/O submission queues and the corresponding I/O completion queue of the I/O completion queues; and
accessing the I/O submission queues and the I/O completion queues to process I/O commands, the accessing based on:
i) the preserved memory addresses of the I/O completion queues;
ii) the preserved memory addresses of the I/O submission queues; and
iii) the preserved mapping between each I/O submission queue of the I/O submission queues and the corresponding I/O completion queue of the I/O completion queues.
11. The method of claim 10 , wherein:
the memory addresses of the I/O submission queues, the memory addresses of the I/O completion queues, and the mapping between each I/O submission queue of the I/O submission queues and the corresponding I/O completion queue of the I/O completion queues are preserved after the partial reset in memory that is accessible to the non-volatile memory controller.
12. The method of claim 11 , wherein:
the memory addresses of the I/O submission queues, the memory addresses of the I/O completion queues, and the mapping between each I/O submission queue of the I/O submission queues and the corresponding I/O completion queue of the I/O completion queues are preserved after the partial reset in memory that is accessible to a host controller that performs the initialization of the non-volatile memory controller.
13. The method of claim 12 , further comprising:
after the partial reset, resetting memory at the memory addresses of the I/O submission queues and the memory addresses of the I/O completion queues prior to submitting I/O commands to the I/O submission queues.
14. The method of claim 13 , wherein accessing the I/O submission queues and the I/O completion queues to process I/O commands after the partial reset comprises:
after the memory at the I/O submission queues has been reset, accessing I/O commands from the I/O submission queues; and
after the memory at the I/O completion queues has been reset, placing responses to the I/O commands.
15. The method of claim 10 , further comprising:
during the initialization of the non-volatile memory controller, establishing an interrupt coalescing feature; and
after the partial reset of the non-volatile memory controller, persisting the interrupt coalescing feature.
16. A non-volatile storage device comprising:
non-volatile memory cells;
memory controller means for controlling read and write access to the non-volatile memory cells;
queue creating means for creating software I/O (Input/Output) submission queues and software I/O completion queues at addresses in memory, the queue creating means further for sending the memory controller means the memory addresses of the software I/O submission queues and the memory addresses of the software I/O completion queues, the queue creating means further for sending the memory controller means a mapping between each software I/O submission queue of the software I/O submission queues and a corresponding software I/O completion queue of the software I/O completion queues;
partial reset triggering means for triggering a partial reset of the memory controller means after the memory addresses of the software I/O submission queues, the memory addresses of the software I/O completion queues, and the mapping between each software I/O submission queue of the software I/O submission queues and the corresponding software I/O completion queue of the software I/O completion queues have been sent to the memory controller means; and
queue clearing means for clearing content of the software I/O submission queues and the software I/O completion queues as a part of the partial reset of the memory controller means;
wherein the memory controller means further comprises:
pointer resetting means for resetting head pointers and tail pointers of the software I/O submission queues and for resetting head pointers and tail pointers of the software I/O completion queues as a part of the partial reset;
partial reset manager means for persisting the following across the partial reset of the memory controller means:
i) the memory addresses of the software I/O submission queues;
ii) the memory addresses of the software I/O completion queues, and
iii) the mapping between each software I/O submission queue of the software I/O submission queues and the corresponding software I/O completion queue of the software I/O completion queues;
command access means for accessing I/O commands from the software I/O submission queues after the content of the software I/O submission queues was cleared, the command access means further for accessing the I/O commands based on the persisted memory addresses of the software I/O submission queues; and
command response means for placing responses to the I/O commands after the content of the software I/O submission completion was cleared, the command response means further for placing the responses to the I/O commands based on the persisted memory addresses of the software I/O completion queues and the persisted mapping between each software I/O submission queue of the software I/O submission queues and the corresponding software I/O completion queue of the software I/O completion queues.
17. The non-volatile storage device of claim 16 , wherein the partial reset triggering means is further for writing to a register to trigger the partial reset of the memory controller means.
18. The non-volatile storage device of claim 16 , wherein the partial reset triggering means is further for placing a vendor-specific command on an admin submission queue to trigger the partial reset of the memory controller means.
19. A system, comprising:
a communication interface;
non-volatile memory cells;
a non-volatile memory controller in communication with the non-volatile memory cells and the communication interface; and
a host controller in communication with the non-volatile memory controller via the communication interface, the host controller configured to:
create I/O (Input/Output) submission queues and I/O completion queues at addresses in memory;
send, to the non-volatile memory controller, the memory addresses of the I/O submission queues and the memory addresses of the I/O completion queues;
send, to the non-volatile memory controller, a mapping between each I/O submission queue of the I/O submission queues and a corresponding I/O completion queue of the I/O completion queues;
trigger a partial reset of the non-volatile memory controller, the partial reset instructing the non-volatile memory controller to maintain the memory addresses of the I/O submission queues, the memory addresses of the I/O completion queues, and the mapping between each I/O submission queue of the I/O submission queues and a corresponding I/O completion queue of the I/O completion queues after the partial reset;
responsive to the partial reset of the non-volatile memory controller, clear content of the I/O submission queues and the I/O completion queues; and
after content of the I/O submission queues is cleared, submit I/O commands to the I/O submission queues.
20. The system of claim 19 , wherein the non-volatile memory controller is configured to:
store the memory addresses of the I/O submission queues and the memory addresses of the I/O completion queues;
store the mapping between each I/O submission queue of the I/O submission queues and the corresponding I/O completion queue of the I/O completion queues;
in response to the partial reset of the non-volatile memory controller, reset head pointers and tail pointers of the I/O submission queues and the I/O completion queues;
persist the memory addresses of the I/O submission queues, the memory addresses of the I/O completion queues, and the mappings across the partial reset of the non-volatile memory controller; and
after the partial reset:
use the persisted memory addresses of the I/O submission queues to retrieve the I/O commands from the I/O submission queues; and
use the persisted memory addresses of the I/O completion queues and the persisted mappings to place responses to the I/O commands on the I/O completion queues.