IP Library Granted Patent US 11,776,637
Granted Patent B2
US 11,776,637 · App. 17/592,237 · Granted Oct 3, 2023

Voltage sharing across memory dies in response to a charge pump failure

Inventors: Elliott Rill (San Jose, CA); Daniel Linnen (Naperville, IL); Kirubakaran Periyannan (Saratoga, CA)
Assignee: Western Digital Technologies, Inc.
G11C16/30G11C5/145
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 11,776,637
App. No.
17/592,237
Granted
Oct 3, 2023
Kind
B2
Abstract

A die-to-die voltage sharing process that may be implemented to overcome a charge pump failure on a memory die of a non-volatile storage device. When a charge pump failure is detected, a controller causes another memory die with a functional charge pump to generate and supply a voltage to the memory die with the failed charge pump. When the voltage is received by the memory die with the failed charge pump, the voltage may be used to perform a requested memory operation.

Claims (39)

1. A method, comprising:

detecting failure of a charge pump on a first NAND die;

identifying a second NAND die that is electrically coupled to the first NAND die;

providing instructions to the second NAND die that causes the second NAND die to generate a voltage for the first NAND die;

providing instructions to the second NAND die that causes the second NAND die to provide the voltage to the first NAND die;

providing instructions to the first NAND die that causes the first NAND die to accept the voltage from the second NAND die; and

causing a memory operation to be performed on the first NAND die in response to the first NAND die receiving the voltage from the second NAND die.

2. The method of claim 1 , wherein the memory operation is a read operation.

3. The method of claim 1 , further comprising:

determining an outcome of the memory operation; and

in response to the determination of the outcome of the memory operation, causing an additional voltage to be provided to the first NAND die.

4. The method of claim 3 , wherein the additional voltage is provided to the first NAND die by the second NAND die.

5. The method of claim 3 , wherein the additional voltage is provided to the first NAND die by a third NAND die, the third NAND die being electrically coupled to the first NAND die.

6. The method of claim 1 , further comprising determining whether to cause the second NAND die to continue providing voltage to the first NAND die.

7. The method of claim 6 , wherein the determination of whether to cause the second NAND die to continue providing voltage to the first NAND die is based, at least in part, on an outcome of the memory operation.

8. A storage device, comprising:

a non-volatile storage unit comprising a first memory die and a second memory die, each of the first memory die and the second memory die comprising a charge pump; and

a controller communicatively coupled to the non-volatile storage unit and configured to:

detect a failure of the charge pump on the first memory die;

cause the charge pump of the second memory die to generate a voltage for the first memory die; and

cause the second memory die to provide the generated voltage to the first memory die.

9. The storage device of claim 8 , wherein the controller is further configured to cause the first memory die to accept the voltage from the second memory die.

10. The storage device of claim 8 , wherein the controller is further configured to cause the first memory die to deactivate its charge pump.

11. The storage device of claim 8 , wherein the controller is further configured to determine whether the generated voltage supplied by the second memory die enables the second memory die to complete a memory operation.

12. The storage device of claim 8 , wherein the voltage from the second memory die supplements a voltage generated by the charge pump of the first memory die.

13. The storage device of claim 8 , further comprising a third memory die, the third memory die comprising a charge pump and wherein the controller is further configured to:

cause the charge pump of the third memory die to generate a voltage for the first memory die; and

cause the third memory die to provide the generated voltage to the first memory die.

14. The storage device of claim 13 , wherein the voltage generated by the charge pump of the third memory die supplements the voltage generated by the charge pump of the second memory die.

15. The storage device of claim 8 , wherein the controller is further configured to determine whether to cause the second memory die to continue providing the voltage to the first memory die.

16. The storage device of claim 8 , wherein the controller is further configured to determine whether to cause the charge pump of the second memory die to increase the generated voltage for the first memory die.

17. A storage device, comprising:

a non-volatile storage unit comprising a first memory die electrically coupled to a second memory die, the first memory die and the second memory die comprising means for generating a voltage;

means for detecting a voltage generating failure on the first memory die;

means for causing the voltage generating means of the second memory die to generate a voltage for the first memory die; and

means for causing the second memory die to provide the generated voltage to the first memory die.

18. The storage device of claim 17 , wherein the means for detecting the failure on the first memory die is a voltage monitoring means associated with the first memory die.

19. The storage device of claim 17 , wherein the failure on the first memory die is a failure of the voltage generating means of the first memory die.

20. The storage device of claim 17 , further comprising means for causing the generated voltage from the second memory die to supplement a voltage generated by the voltage generating means of the first memory die.

Assignments (8)
PARTIAL RELEASE OF SECURITY INTERESTS Recorded Apr 25, 2025
From: JPMORGAN CHASE BANK, N.A., AS AGENT
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 071382/0001 →
SECURITY AGREEMENT Recorded Apr 25, 2025
From: SANDISK TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 071050/0001 →
PATENT COLLATERAL AGREEMENT Recorded Aug 23, 2024
From: SANDISK TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS THE AGENT
Reel/Frame 068762/0494 →
CHANGE OF NAME Recorded Jun 27, 2024
From: SANDISK TECHNOLOGIES, INC.
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 067982/0032 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 29, 2024
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 067567/0682 →
PATENT COLLATERAL AGREEMENT - A&R LOAN AGREEMENT Recorded Aug 21, 2023
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A.
Reel/Frame 064715/0001 →
PATENT COLLATERAL AGREEMENT - DDTL LOAN AGREEMENT Recorded Aug 21, 2023
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A.
Reel/Frame 067045/0156 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 3, 2022
From: RILL, ELLIOTT; LINNEN, DANIEL; PERIYANNAN, KIRUBAKARAN
To: WESTERN DIGITAL TECHNOLOGIES, INC.
Reel/Frame 058881/0990 →