Enhanced digital signal processor (DSP) NAND flash
A method and apparatus for systems and methods for digital signal processing (DSP) in a non-volatile memory (NVM) device comprising CMOS coupled to NVM die, of a data storage device. According to certain embodiments, one or more DSP calculations are provided by a controller to the CMOS components of the NVM, that configure one or more memory die to carry out atomic calculations on the data resident on the die. The results of calculations of each die are provided to an output latch for each die, back-propagating data back to the configured calculation portion as needed, otherwise forwarding the results to the controller. The controller aggregates the results of DSP calculations of each die and presents the results to the host system.
1. A data storage device, comprising:
a memory device comprising a plurality of CMOS structures, each CMOS structure coupled to a portion of an NVM die; and
a controller configured to cause the data storage device to:
receive a command to perform a digital signal processing (DSP) computation;
encode a portion of the DSP computation to each CMOS structure of the plurality of CMOS structures of the memory device; and
receive an output of the DSP computation from the plurality of CMOS structures of the memory device.
2. The data storage device of claim 1 , wherein the CMOS structure encodes a portion of the NVM to calculate the portion of the DSP computation, and wherein the encoding by one or more CMOS structures of the plurality of CMOS structures occurs in parallel.
3. The data storage device of claim 2 , wherein the NVM calculates the portion of the DSP computation, using data stored on the NVM.
4. The data storage device of claim 3 , wherein the CMOS structure encodes a portion of the NVM as one of a multiply-accumulate unit (MAC), an arithmetic logic unit (ALU), or a central processing unit (CPU).
5. The data storage device of claim 4 , wherein the DSP computation comprises one of filtering, searching, counting, compression, image analysis, a mathematical transformation, or forming a machine learning neuron.
6. The data storage device of claim 5 , comprising a second memory device, the controller further configured to encode a portion of the DSP computation to the second memory device and receive a second output of the DSP computation from the second memory device.
7. The data storage device of claim 6 , the controller further configured to aggregate the output and second output in response to the command.
8. A controller for a data storage device, comprising:
a memory device comprising computer-readable instructions; and
a processor configured to read the computer-readable instructions that cause the processor to execute a method for digital signal processing, the method comprising:
storing a portion of data of a data set on an NVM die of a plurality of NVM dies, the portion of data comprising an atomic unit of data;
receiving a digital signal processing (DSP) command comprising a plurality of calculations;
encoding a CMOS of an NVM memory device comprising the CMOS coupled to an NVM die of the plurality of NVM dies, with a calculation of the plurality of calculations;
processing the calculation on the NVM die with the portion of data stored on the NVM die; and
receiving a result of processing the calculation.
9. The controller of claim 8 , the method further comprising:
storing a second portion of data of the data set on a second NVM die of the plurality of NVM dies, the second NVM die coupled to the CMOS; and
processing the calculation on the second NVM die.
10. The controller of claim 9 , wherein the processing the calculation includes receiving a result of processing the calculation of the second NVM die.
11. The controller of claim 10 , wherein the CMOS encodes a portion of the NVM die with the calculation, comprising one of a multiply-accumulate unit (MAC), an arithmetic logic unit (ALU), or a central processing unit (CPU).
12. The controller of claim 11 , wherein the DSP command comprises one of forming a machine learning neuron, a mathematical transformation, image analysis, counting, searching, or filtering.
13. The controller of claim 8 , wherein storing the portion of data of the data set comprises storing according to one of a zoned namespace, a key value pair, a stream, an endurance group/NVM set, and a device-internal file system of the controller.
14. The controller of claim 8 , further comprising back-propagating a portion of the result of processing the calculation to the NVM.
15. The controller of claim 10 , the method further comprising providing the result of processing the calculation to an output latch of the NVM.
16. A data storage device comprising:
a memory means; and
a controller means configured to perform a method for digital signal processing (DSP) comprising:
receiving a command to perform a DSP calculation comprising a plurality of atomic calculation components;
encoding a plurality of dies of the memory means, each die encoded to calculate at least one of the plurality of atomic calculation components; and
receiving an output of the DSP calculation.
17. The data storage device of claim 16 , the method further comprising the controller means aggregating output of each encoded die.
18. The data storage device of claim 17 , wherein encoding the plurality of die of the memory means comprises encoding at least one of the plurality of die to function as a multiply-accumulate unit (MAC), an arithmetic logic unit, or a central processing unit (CPU).
19. The data storage device of claim 18 , wherein the DSP calculation comprises one of filtering, searching, counting, compression, image analysis, mathematical transformation, or machine learning.
20. The data storage device of claim 19 , the method further comprising providing the output of the DSP calculation for one of the plurality of die of the memory means to an output latch, and back-propagating contents of the output latch back to the one of the plurality of die of the memory means.