Methods for early write termination with non-volatile memory
View Patent ↗In one embodiment of the invention, a memory apparatus for improved write performance is disclosed. The memory apparatus includes a base printed circuit board (PCB) having an edge connector for plugging into a host server system; a card level power source to provide card level power during a power failure; a memory controller coupled to the card level power source and having one or more memory channels; and one or more non-volatile memory devices (NVMDs) coupled to the card level power source and organized to respectively couple to the memory channels controlled by the memory controller. Each memory controller provides queuing and scheduling of memory operations on a channel for each NVMD in the memory channels. Responsive to power failure, the memory controller receives card level power and changes the scheduling of memory operations to the NVMDs in each memory channel.
1. A low power computer server with non-volatile solid state storage, the low power computer server comprising:
a printed circuit board having a plurality of wire traces;
a plurality of sockets mounted to the printed circuit board each to receive a connector of a server memory card;
a plurality of master memory controllers mounted to the printed circuit board and coupled to the plurality of sockets;
dynamic random access memory (DRAM) mounted to the printed circuit board and coupled to the plurality of master memory controllers;
a plurality of processors mounted to the printed circuit board coupled to the plurality of master memory controllers;
a plurality of server memory cards having a plurality of connectors coupled to the plurality of sockets, each of the plurality of server memory cards including
a base printed circuit board with a plurality of wire traces;
a connector coupled to the plurality of wire traces;
a card level power source coupled to the base printed circuit board; and
a plurality of non-volatile memory devices (NVMDs) coupled to the base printed circuit board;
wherein in response to a power failure, the one or more non-volatile memory devices are coupled to and receive the card level power source to assure one or more pending memory operations can be completed before the card level power source is depleted below operating power levels.
2. The lower power computer server of claim 1 , wherein each of the plurality of server memory cards further includes
one or more slave memory controllers mounted to the base printed circuit board, the one or more slave memory controllers having a plurality of memory channels coupled to the plurality of NVMDs,
wherein in response to a power failure, the one or more slave memory controllers couple to and receive the card level power source and rearrange scheduling of memory operations with the plurality of NVMDs in each of the one or more memory channels to assure the one or more pending memory operations can be completed before the card level power source is depleted below operating power levels.
3. The lower power computer server of claim 2 , each memory controller includes
one or more channel controller to control queuing and scheduling of memory operations to the NVMDs in the channel, each of the one or more channel controllers including one or more backup location registers associated with each NVMD in the channel; and
a shared buffer pool coupled to the one or more channel controllers, the storage locations of the shared buffer pool shared amongst the one or more channel controllers; and
wherein in response to a failed write of data from a first location in the shared buffer pool to a first NVMD address, the channel controller to rewrite the data from the first location into a first NVMD backup address pointed to by a first backup location register.
4. The lower power computer server of claim 3 , wherein
in response to a successful write of data from the first location to the first NVMD backup address, the channel controller to provide an indicator that the write of data was successful and data was stored into the first NVMD backup address.