IP Library Granted Patent US 11,656,789
Granted Patent B2
US 11,656,789 · App. 17/412,158 · Granted May 23, 2023

Asymmetric read sense

Inventors: Jonas Goode (Lake Forest, CA); Richard Galbraith (Rochester, MN); Henry Yip (Bellflower, CA); Vinh Hoang (Laguna Hills, CA)
Assignee: Western Digital Technologies, Inc.
G06F3/0655G06F3/0604G06F3/0679G11C7/06G11C29/50004
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Quick Facts
Patent No.
US 11,656,789
App. No.
17/412,158
Granted
May 23, 2023
Kind
B2
Abstract

A data storage device includes a memory device including a plurality of wordlines, each including a plurality of cells, and a cell statistics generator (CSG) disposed on the memory device. The CSG includes logic configured to receive a first read sense at a threshold voltage of one or more threshold voltages of each cell of a wordline of the plurality of wordlines, determine that a second read sense is required based on the first read sense, receive the second read sense, determine a deviation parameter and a dispersion parameter for an asymmetric adjustment of the left threshold voltage and the right threshold voltage, and adjust the left threshold voltage and the right threshold voltage based on the deviation parameter and the dispersion parameter. The second read sense includes a plurality of left read senses at a left threshold voltage and a plurality of right senses at a right threshold voltage.

Claims (48)

1. A data storage device, comprising:

a memory device comprising a plurality of wordlines, each comprising a plurality of cells; and

a cell statistics generator (CSG) disposed on the memory device, the CSG comprising logic configured to:

receive a first read sense at a threshold voltage of one or more threshold voltages of each cell of a wordline of the plurality of wordlines;

determine that a second read sense is required based on the first read sense, wherein the second read sense comprises a plurality of left senses at a left threshold voltage and a plurality of right senses at a right threshold voltage;

determine a deviation parameter and a dispersion parameter for an asymmetric adjustment of the left threshold voltage and the right threshold voltage; and

adjust the left threshold voltage and the right threshold voltage based on the deviation parameter and the dispersion parameter.

2. The data storage device of claim 1 , wherein the logic is further configured to sum, for the wordline, each of the plurality of left senses and sum, for the wordline, each of the plurality of right senses and subtract an expectation constant from each of the sums.

3. The data storage device of claim 2 , wherein the deviation parameter is a sum of the sum of the plurality of left senses and the sum of the plurality of right senses, and wherein the dispersion parameter is a difference between the sum of the plurality of left senses and the sum of the plurality of right senses.

4. The data storage device of claim 3 , wherein the logic is further configured to, based on the deviation parameter, either:

increase the left threshold voltage and the right threshold voltage; or

decrease the left threshold voltage and the right threshold voltage.

5. The data storage device of claim 3 , wherein the logic is further configured to, based on the dispersion parameter, either:

shift the left threshold voltage and the right threshold voltage closer to the threshold voltage; or

shift the left threshold voltage and the right threshold voltage further from the threshold voltage.

6. The data storage device of claim 1 , wherein the logic is further configured to:

receive the plurality of left senses and the plurality of right senses;

adjust the left threshold voltage and the right threshold voltage by the deviation parameter and the dispersion parameter; and

re-receive the plurality of left senses and the plurality of right senses.

7. The data storage device of claim 6 , wherein the logic is further configured to re-receive the plurality of left senses and the plurality of right senses based on an adjusted left threshold voltage and an adjusted right threshold voltage more than once.

8. The data storage device of claim 7 , wherein the logic is further configured to, upon re-receiving the plurality of left senses and the plurality of right senses:

determine whether further adjusting of the left threshold voltage and the right threshold voltage is needed based on a number of bit flips;

based on determining that further adjusting is needed, re-determine the deviation parameter and the dispersion parameter; and

based on the re-determining, re-adjust the left threshold voltage and the right threshold voltage by the deviation parameter and the dispersion parameter.

9. A data storage device, comprising:

a memory device comprising a plurality of wordlines, each comprising a plurality of cells; and

a cell statistics generator (CSG) disposed on the memory device, the CSG comprising logic configured to:

receive a plurality of left read senses and a plurality of right read senses for a threshold voltage of a plurality of threshold voltages for each cell of the plurality of cells of a wordline of the plurality of wordlines;

sum a plurality of received left read senses and a plurality of right read senses, wherein an expectation value is subtracted from the summed plurality of received left read senses and the summed plurality of right read senses;

calculate a deviation parameter and a dispersion parameter; and

asymmetrically adjust the plurality of left read senses and the plurality of right read senses based on the deviation parameter and the dispersion parameter.

10. The data storage device of claim 9 , wherein the CSG comprises a first adder and a second adder, wherein the first adder is configured to sum the plurality of received left read senses and subtract the expectation value from the summed plurality of received left read senses, and wherein the second adder is configured to sum the plurality of received right read senses and subtract the expectation value from the summed plurality of right read senses.

11. The data storage device of claim 10 , wherein the CSG further comprises a third adder and a fourth adder, wherein the third adder is configured to sum a first plurality of results from the first adder, and wherein the fourth adder is configured to sum a second plurality of results from the second adder.

12. The data storage device of claim 11 , wherein the CSG further comprises a first combiner and a second combiner, wherein the first combiner is configured to calculate the deviation parameter, and wherein the second combiner is configured to calculate the dispersion parameter.

13. The data storage device of claim 12 , wherein the deviation parameter is calculated by summing a first sum of the third adder and a second sum of the fourth adder.

14. The data storage device of claim 12 , wherein the dispersion parameter is calculated by subtracting a first sum of the third adder from a second sum of the fourth adder.

15. The data storage device of claim 9 , wherein the logic is configured to adjust a bin spacing of the left read sense and the right read sense based on the dispersion parameter.

16. The data storage device of claim 9 , wherein the logic is configured to subtract a voltage value or adds a voltage value to both the voltage of the left read sense and the voltage of the right read sense based on the deviation parameter.

17. A data storage device, comprising:

memory means comprising a plurality of wordlines, each comprising a plurality of cells; and

one or more cell statistics generators (CSGs) disposed on the memory means, the one or more CSGs each comprising logic configured to:

receive a plurality of left read senses at a first voltage from a threshold voltage of each cell of a wordline of the plurality of wordlines, wherein the first voltage is substantially less than the threshold voltage;

receive a plurality of right read senses at a second voltage from the threshold voltage, wherein the second voltage is substantially greater than the threshold voltage, and wherein the first voltage and the second voltage are offset by a substantially equal voltage from the threshold voltage;

determine a deviation parameter and a dispersion parameter to asymmetrically adjust the first voltage and the second voltage; and

adjust the first voltage and the second voltage based on the deviation parameter and the dispersion parameter.

18. The data storage device of claim 17 , wherein the receiving the plurality of left read senses, the receiving the plurality of right read senses, and the determining occurs more than once.

19. The data storage device of claim 17 , wherein the logic is further configured to determine a number of bit flips of the plurality of left read senses and the plurality of right read senses.

20. The data storage device of claim 19 , wherein the logic is further configured to determine a first voltage shift for the left read sense and a second voltage shift for the right read sense upon determining that the number of bit flips of either the plurality of left read senses, the plurality of right read senses, or both the plurality of left read senses and the plurality of right read senses is greater than a threshold value.

Assignments (10)
PARTIAL RELEASE OF SECURITY INTERESTS Recorded Apr 25, 2025
From: JPMORGAN CHASE BANK, N.A., AS AGENT
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 071382/0001 →
SECURITY AGREEMENT Recorded Apr 25, 2025
From: SANDISK TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 071050/0001 →
PATENT COLLATERAL AGREEMENT Recorded Aug 23, 2024
From: SANDISK TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS THE AGENT
Reel/Frame 068762/0494 →
CHANGE OF NAME Recorded Jun 27, 2024
From: SANDISK TECHNOLOGIES, INC.
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 067982/0032 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 29, 2024
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 067567/0682 →
PATENT COLLATERAL AGREEMENT - A&R LOAN AGREEMENT Recorded Aug 21, 2023
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A.
Reel/Frame 064715/0001 →
PATENT COLLATERAL AGREEMENT - DDTL LOAN AGREEMENT Recorded Aug 21, 2023
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A.
Reel/Frame 067045/0156 →
RELEASE OF SECURITY INTEREST AT REEL 058426 FRAME 0815 Recorded Feb 8, 2022
From: JPMORGAN CHASE BANK, N.A.
To: WESTERN DIGITAL TECHNOLOGIES, INC.
Reel/Frame 058965/0679 →
SECURITY INTEREST Recorded Dec 9, 2021
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS AGENT
Reel/Frame 058426/0815 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 26, 2021
From: GOODE, JONAS; GALBRAITH, RICHARD; YIP, HENRY; HOANG, VINH
To: WESTERN DIGITAL TECHNOLOGIES, INC.
Reel/Frame 057297/0287 →