IP Library Granted Patent US 10,331,555
Granted Patent B1
US 10,331,555 · App. 15/913,914 · Granted Jun 25, 2019

Dynamic memory compaction

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Quick Facts
Patent No.
US 10,331,555
App. No.
15/913,914
Granted
Jun 25, 2019
Kind
B1
Abstract

Apparatus, systems, methods, and computer program products for dynamic memory compaction are disclosed. A memory device comprises a plurality of memory blocks and a controller for the memory device. A controller is configured to generate an input/output command to write a data chunk to a first memory block of a plurality of memory blocks. A controller is configured to compact an amount of valid data in a second memory block of a plurality of memory blocks based on a size of an I/O command.

Claims (77)

1. An apparatus comprising:

a memory device comprising a plurality of memory blocks; and

a controller for the memory device, the controller configured to:

generate an input/output (I/O) command to write a data chunk to a first memory block of the plurality of memory blocks, and

compact a first amount of valid data stored in a second memory block of the plurality of memory blocks based on a size of the data chunk of the I/O command.

2. The apparatus of claim 1 , wherein:

the first memory block and the second memory block each comprise single level cell (SLC) blocks; and

the I/O command comprises a write command to write new data to the memory device.

3. The apparatus of claim 1 , wherein:

the controller is further configured to:

accumulate compacted valid data in a buffer, and

write the accumulated compacted valid data to a third memory block of the plurality of memory blocks;

the third memory block comprises a single level cell (SLC) block; and

compacting the valid data and writing the accumulated compacted data comprise at least a portion of a garbage collection process.

4. The apparatus of claim 1 , wherein:

a third memory block in the plurality of memory block stores the data chunk;

the third memory block comprises a single level cell (SLC) block;

the first memory block comprises a multi-level cell (MLC) block storing two or more bits per cell; and

the I/O command comprises a fold command to write the first data chunk from an SLC block to an MLC block.

5. The apparatus of claim 1 , wherein:

the controller is further configured to:

accumulate compacted valid data in a buffer, and

write the accumulated compacted valid data to a third memory block of the plurality of memory blocks;

the third memory block comprises an MLC block storing two or more bits per cell; and

compacting the valid data and writing the accumulated compacted data comprise at least a portion of a garbage collection process.

6. The apparatus of claim 1 , wherein the first amount of valid data is one of:

less than the size of the data chunk of the I/O command; and

equal to the size of the data chunk of the I/O command.

7. The apparatus of claim 1 , wherein the first amount of valid data is proportional to a size of the data chunk of the I/O command.

8. The apparatus of claim 1 , wherein the controller is further configured to:

determine the size of the data chunk of the I/O command; and

calculate the first amount of valid data for compaction (AVDC 1 ) in accordance with a ratio of valid fragments (VF) and total fragments (TF) in the first memory block multiplied by the size (S 2 ) of the data chunk of the first I/O command such that AVDC 1 =(VF/TF)*S 2 .

9. The apparatus of claim 1 , wherein the controller is further configured to:

determine a quantity of failed fragments in the first amount of valid data in response to detecting a compaction error when compacting the first amount of valid data;

generate a second I/O command to write a second data chunk to the memory device, determine a second size of the second I/O command; and

compact a second amount of valid data in the first memory block based on the second size of the second I/O command and the quantity of failed fragments.

10. The apparatus of claim 9 , wherein the controller is further configured to calculate the second amount of valid data for compaction (AVDC 2 ) in accordance with a ratio of valid fragments (VF) plus the quantity of failed fragments (FF) and total fragments (TF) in the first memory block multiplied by the second size (S 2 ) of the second I/O command such that AVDC 2 =[(VF+FF)/TF]*S 2 .

11. A method comprising:

generating, by a controller, an input/output (I/O) command to write a data chunk to a first memory block of a plurality of memory blocks in a memory device; and

in response to the I/O command, performing a garbage collection process, wherein:

at least a compaction portion of the garbage collection process is based on a first size of the data chunk.

12. The method of claim 11 , wherein the compaction portion of the garbage collection process compacts an amount of valid data in a set of memory blocks of the plurality of memory blocks based on the first size of the data chunk to generate a compacted amount of valid data.

13. The method of claim 12 , wherein the garbage collection process further comprises:

accumulating the first compacted amount of valid data and a second compacted amount of valid data to generate an accumulated amount of compacted valid data; and

writing an amount of the accumulated amount of compacted valid data to a second memory block of the plurality of memory blocks,

wherein the amount of the accumulated amount of compacted valid data is based on a ratio of valid data to total data in the first memory block multiplied by the first size of the data chunk.

14. The method of claim 13 , wherein:

the first memory block, the second memory block, and the set of memory blocks each comprise a single level cell (SLC) block; and

the I/O command is a write command to write new data to the memory device.

15. The method of claim 14 , wherein:

the data chunk is stored in a third memory block of the plurality of memory blocks;

the third memory block comprises a single level cell (SLC) block;

the first memory block, the second memory block, and the set of memory blocks each comprise a multi-level cell (MLC) block storing two or more bits per cell; and

the amount of the accumulated amount of compacted valid data is written from a set of SLC blocks to an MLC block in response to a fold command.

16. The method of claim 12 , wherein the amount of valid data (AVDC) is calculated in accordance with a ratio of valid fragments (VF) and total fragments (TF) in the set of memory blocks multiplied by the first size (S 1 ) of the data chunk in the I/O command such that AVDC=(VF/TF)*S 1 .

17. The method of claim 12 , further comprising:

determining a quantity of failed fragments (FF) in the compacted amount of valid data in response to detecting a compaction error when compacting the amount of valid data;

receiving a subsequent I/O command to write a subsequent data chunk to the memory device; and

determining a second size of the subsequent data chunk, wherein:

the compaction portion of the garbage collection process further comprises calculating a compensating amount of valid data (CAVDC) including a ratio of valid fragments (VF) plus FF and total fragments (TF) in the set of memory blocks multiplied by the second size (S 2 ) of the subsequent data chunk in the subsequent I/O command such that CAVDC=[(VF+FF)/TF]*S 2 .

18. An apparatus comprising:

means for generating an input/output (I/O) command to write a data chunk to a memory device;

means for determining a size of the data chunk; and

means for compacting an amount of valid data in a plurality of memory blocks of the memory device based on the size of the data chunk.

19. The apparatus of claim 18 , further comprising:

means for accumulating the compacted amount of valid data and a second compacted amount of valid data to generate an accumulated amount of compacted valid data; and

means for writing an amount of the accumulated amount of compacted valid data to a different memory block of the plurality of memory blocks,

wherein the amount of the accumulated amount of compacted valid data is based on a ratio of the valid data to a total amount of data in the plurality of memory blocks multiplied by the size of the data chunk.

20. The apparatus of claim 18 , wherein the amount of valid data is one of:

proportional to a size of the data chunk of the I/O command;

less than the size of the data chunk of the I/O command; and

equal to the size of the data chunk of the I/O command.

21. An apparatus comprising:

a memory device comprising a plurality of memory blocks; and

a controller for the memory device, the controller configured to:

generate an input/output (I/O) command to write a data chunk to a first memory block of the plurality of memory blocks, and

write back an amount of valid data stored in a second memory block of the plurality of memory blocks to another memory block of the plurality of memory blocks that only stores valid data based on a size of the data chunk of the I/O command.

Assignments (10)
PARTIAL RELEASE OF SECURITY INTERESTS Recorded Apr 25, 2025
From: JPMORGAN CHASE BANK, N.A., AS AGENT
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 071382/0001 →
SECURITY AGREEMENT Recorded Apr 25, 2025
From: SANDISK TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 071050/0001 →
PATENT COLLATERAL AGREEMENT Recorded Aug 23, 2024
From: SANDISK TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS THE AGENT
Reel/Frame 068762/0494 →
CHANGE OF NAME Recorded Jun 27, 2024
From: SANDISK TECHNOLOGIES, INC.
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 067982/0032 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 29, 2024
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 067567/0682 →
PATENT COLLATERAL AGREEMENT - A&R LOAN AGREEMENT Recorded Aug 21, 2023
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A.
Reel/Frame 064715/0001 →
PATENT COLLATERAL AGREEMENT - DDTL LOAN AGREEMENT Recorded Aug 21, 2023
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A.
Reel/Frame 067045/0156 →
RELEASE OF SECURITY INTEREST AT REEL 052915 FRAME 0566 Recorded Feb 8, 2022
From: JPMORGAN CHASE BANK, N.A.
To: WESTERN DIGITAL TECHNOLOGIES, INC.
Reel/Frame 059127/0001 →
SECURITY INTEREST Recorded Feb 6, 2020
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS AGENT
Reel/Frame 052915/0566 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 27, 2018
From: MUTHIAH, RAMANATHAN; RAMAMURTHY, RAMKUMAR; VENKATARAMANAN, BALAJI THRAKSHA
To: WESTERN DIGITAL TECHNOLOGIES, INC.
Reel/Frame 047158/0108 →
Cited By (2)
US 12,572,302 US 12,625,639