Method using logical based addressing for latency reduction
View Patent ↗A method for control of latency information through logical block addressing is described comprising receiving a computer command, performing a read flow operation on a computer buffer memory based on the computer command; populating at least one metadata frame with data based on logical block address latency information; initiating a serial attached data path transfer for one of transmitting and receiving data to the computer drive and transmitting data to a host based on the second latency.
1. A method for control of latency information through logical block addressing, comprising:
receiving a computer command that has been dispatched to a flash translation layer of a computer drive wherein a computer arrangement is operating at a first latency;
performing a read flow operation on a computer buffer memory based on the computer command;
populating at least one metadata frame with data based on logical block address latency information, wherein the at least one metadata frame is a serial attached SCSI data frame;
initiating a data transfer for one of transmitting and receiving data to the computer drive;
reading the at least one metadata frame;
operating the computer arrangement at a second latency, different than the first latency, based on the at least one metadata frame; and
transmitting data to a host based on the second latency.
2. The method according to claim 1 , wherein the logical block address latency information is provided by the computer drive, wherein the computer drive is a solid state drive.
3. The method according to claim 2 , wherein the logical block address latency information includes a provisioning status.
4. The method according to claim 2 , wherein the logical block address latency information includes a caching status.
5. The method according to claim 2 , wherein the logical block address latency information includes an unmapped pattern type.
6. The method according to claim 2 , wherein the logical block address latency information includes erase and program collision information.
7. The method according to claim 2 , wherein the logical block address latency information includes a latency score.
8. The method according to claim 2 , wherein the logical block address latency information includes an error recovery status.
9. The method according to claim 2 , wherein the logical block address latency information includes a restricted reordering collision information.
10. The method according to claim 1 , wherein the at least one metadata frame is a verbose descriptor arrangement.
11. The method according to claim 1 , wherein the at least one metadata frame is configured to address multiple data blocks.
12. The method according to claim 1 , wherein the at least one metadata frame is configured to provide an external analyzer trigger.
13. The method according to claim 1 wherein the at least one metadata frame is configured to provide device internal system debug information.
14. The method according to claim 1 , further comprising:
receiving the data at the host.
15. The method according to claim 14 , further comprising:
adapting activities of the host based on the received data.
16. The method according to claim 15 , further comprising:
displaying latency data to a user.
17. The method according to claim 1 , further comprising:
receiving host latency information from the host at the computer drive.
18. The method according to claim 17 , further comprising:
operating the computer drive according to the host latency information.
19. The method according to claim 1 , wherein the computer drive is a solid state drive.
20. The method according to claim 1 , wherein the computer arrangement is a personal computer.
21. The method according to claim 1 , wherein the computer arrangement is a server.
22. An arrangement comprising:
means for receiving a computer command that has been dispatched to a flash translation layer of a solid state drive wherein a computer arrangement is operating at a first latency;
means for performing a read flow operation on a computer buffer memory based on the computer command;
means for populating at least one metadata frame with data based on logical block address latency information, wherein the at least one metadata frame is a serial attached SCSI data frame;
means for initiating a serial attached data path transfer for one of transmitting and receiving data to the solid state drive;
means for reading the at least one metadata frame;
means for modifying the computer such that the computer operates at a second latency, different than the first latency, based on the at least one metadata frame; and
means for transmitting data to a host based on the second latency.
23. A method for control of latency through logical block addressing, comprising:
receiving a computer command at a computer drive flash translation layer operating at a first latency;
performing an operation on a computer buffer memory based on the computer command;
populating at least one metadata frame with logical block address latency information, wherein the at least one metadata frame is a serial attached SCSI data frame;
initiating one transmitting and receiving data to the computer drive;
reading the at least one metadata frame;
operating the computer drive at a second latency, different than the first latency, based on the at least one metadata frame; and
transmitting data to a host at the second latency.
24. The method according to claim 23 , wherein the operation is a read operation.
25. The method according to claim 23 , wherein the logical block address latency information includes a provisioning status.