Dual time domain control for dynamic staggering
Aspects of a storage device including a memory and a controller are provided. The memory can include memory dies that draw a current from a current source during a program operation. The controller may monitor for an alarm signal from the memory dies on a first common channel between the controller and the memory dies. The alarm signal indicates that a corresponding memory die is entering an operational state that draws a peak current from the current source for the program operation. The controller can receive, from the memory dies, one or more alarm signals on the first common channel within a predetermined threshold time. The controller can transmit a postpone signal on a second common channel to the memory dies based on the one or more alarm signals received within the predetermined threshold time.
1. A storage device, comprising:
a memory comprising a plurality of memory dies, wherein each of the plurality of memory dies draws a current from a current source during a program operation; and
a controller coupled to the memory and configured to:
monitor for an alarm signal from one or more of the plurality of memory dies on a first common channel between the controller and the plurality of memory dies, the alarm signal indicating that a corresponding memory die of the plurality of memory dies is entering an operational state that draws a peak current from the current source for the program operation;
receive, from the plurality of memory dies, one or more alarm signals on the first common channel within a predetermined threshold time; and
transmit a postpone signal on a second common channel to the plurality of memory dies based on the one or more alarm signals received within the predetermined threshold time.
2. The storage device of claim 1 , wherein the one or more alarm signals are received at different times within the predetermined threshold time.
3. The storage device of claim 1 , wherein the controller is further configured to:
determine whether the one or more alarm signals received within the predetermined threshold time corresponds to a number of alarm signals that exceeds a threshold number; and
generate the postpone signal when the one or more alarm signals received within the predetermined threshold time corresponds to the number of alarm signals that exceeds the threshold number.
4. The storage device of claim 1 , wherein the postpone signal is broadcast to the plurality of memory dies over the second common channel.
5. The storage device of claim 1 , wherein the predetermined threshold time corresponds to a duration of the peak current drawn by at least one of the plurality of memory dies during the program operation.
6. The storage device of claim 1 , wherein the first common channel and the second common channel correspond to a same signal trace between the controller and the plurality of memory dies.
7. The storage device of claim 1 , wherein the controller is further configured to:
receive a first alarm signal from a first memory die of the plurality of memory dies on the first common channel;
initiate, in response to the first alarm signal, a counter to determine a count value of alarm signals received from the plurality of memory dies;
initiate, in response to the first alarm signal, a timer to measure the predetermined threshold time;
receive a second alarm signal from a second memory die of the plurality of memory dies on the first common channel;
determine whether the second alarm signal is received within the predetermined threshold time;
increment the count value when the second alarm signal is received within the predetermined threshold time;
reset the count value when the second alarm signal is not received within the predetermined threshold time;
determine whether the count value corresponds to a maximum count value;
resume the timer when the count value does not correspond to the maximum count value; and
generate the postpone signal when the count value corresponds to the maximum count value.
8. The storage device of claim 7 , wherein the count value corresponds to a number of the plurality of memory dies that have issued an alarm signal that at least in part overlap with one another within the predetermined threshold time.
9. The storage device of claim 7 , wherein the maximum count value is based on an allowable amount of the peak current to be drawn concurrently by the one or more of the plurality of memory dies for a duration within the predetermined threshold time.
10. The storage device of claim 1 , wherein the postpone signal causes at least one of the plurality of memory dies to delay an ongoing storage operation by a fixed duration when the postpone signal is received at the at least one of the plurality of memory dies within a predetermined timing window following issuance of a corresponding alarm signal.
11. A storage device, comprising:
a memory comprising a plurality of memory dies; and
a controller coupled to the memory and configured to:
monitor for an alarm signal from one or more of the plurality of memory dies on a first common channel between the controller and the plurality of memory dies;
receive, from the plurality of memory dies, one or more alarm signals on the first common channel within a predetermined threshold time; and
transmit a postpone signal on a second common channel to the plurality of memory dies based on the one or more alarm signals received within the predetermined threshold time.
12. The storage device of claim 11 , wherein each of the plurality of memory dies draws a current from a current source during a program operation.
13. The storage device of claim 11 , wherein the alarm signal indicates that a corresponding memory die of the plurality of memory dies is entering an operational state that draws a peak current from a current source for a program operation.
14. The storage device of claim 11 , wherein the controller is further configured to:
determine whether the one or more alarm signals received within the predetermined threshold time corresponds to a number of alarm signals that exceeds a threshold number; and
generate the postpone signal when the one or more alarm signals received within the predetermined threshold time corresponds to the number of alarm signals that exceeds the threshold number.
15. The storage device of claim 11 , wherein the postpone signal is broadcast to the plurality of memory dies over the second common channel.
16. The storage device of claim 11 , wherein the predetermined threshold time corresponds to a duration of a peak current drawn by at least one of the plurality of memory dies during a program operation.
17. A storage device, comprising:
a plurality of memory dies configured to draw a current from a current source during a program operation; and
a controller coupled to the plurality of memory dies and configured to:
monitor for an alarm signal from one or more of the plurality of memory dies on a first common channel between the controller and the plurality of memory dies, the alarm signal indicating that a corresponding memory die of the plurality of memory dies is entering an operational state that draws a peak current from the current source for the program operation;
receive, from the plurality of memory dies, one or more alarm signals on the first common channel within a predetermined threshold time; and
transmit a postpone signal on a second common channel to the plurality of memory dies based on the one or more alarm signals received within the predetermined threshold time.
18. The storage device of claim 17 , wherein the controller is further configured to:
determine whether the one or more alarm signals received within the predetermined threshold time corresponds to a number of alarm signals that exceeds a threshold number; and
generate the postpone signal when the one or more alarm signals received within the predetermined threshold time corresponds to the number of alarm signals that exceeds the threshold number.
19. The storage device of claim 17 , wherein the postpone signal is broadcast to the plurality of memory dies over the second common channel.
20. The storage device of claim 17 , wherein the postpone signal causes at least one of the plurality of memory dies to delay an ongoing storage operation by a fixed duration when the postpone signal is received at the at least one of the plurality of memory dies within a predetermined timing window following issuance of a corresponding alarm signal.