IP Library Granted Patent US 10,296,473
Granted Patent B2
US 10,296,473 · App. 15/651,544 · Granted May 21, 2019

System and method for fast execution of in-capsule commands

Inventor: Shay Benisty (Be'er Sheva, IL)
Assignee: Western Digital Technologies, Inc.
G06F13/1642G06F13/1668
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Quick Facts
Patent No.
US 10,296,473
App. No.
15/651,544
Granted
May 21, 2019
Kind
B2
Abstract

Systems and methods for fast execution of in-capsule commands are disclosed. NVM Express (NVMe) over fabrics is a standard in which a host device sends commands in a command capsule to a memory device. The memory device then saves the command capsule as an entry to a submission queue, and thereafter fetches the command capsule from the submission queue for execution. In certain instances, such as when the command capsule includes a write command, the memory device may decide to by-pass the submission queue and instead begin execution of the command without fetching the command from the submission queue. In these instances of bypassing, the memory device may instead insert a no-operation entry in the submission queue. Further, the memory device may send a response capsule prior to beginning execution of the command.

Claims (64)

1. A method for a memory device to process a command, the method comprising:

in the memory device:

receiving the command from a host device;

analyzing at least one aspect of the command;

determining, based on the analysis, whether to execute the command without fetching the command from a submission queue;

responsive to determining to execute the command without fetching the command from the submission queue;

executing the command without fetching the command from the submission queue; and

placing a command placeholder, instead of the command, in the submission queue;

and

responsive to determining to execute the command with fetching the command from the submission queue:

placing the command in the submission queue;

fetching the command from the submission queue; and

executing the command.

2. The method of claim 1 , wherein the at least one aspect of the command comprises a type of the command.

3. The method of claim 2 , wherein:

the type of the command comprises a write command; and

the method further comprises responsive to determining that the type of the command comprises the write command, determining to execute the command without fetching the command from the submission queue.

4. The method of claim 1 , wherein:

the command placeholder comprises a no-operation entry; and

placing the command in the submission queue comprises placing at least a part of the command in the submission queue.

5. The method of claim 4 , wherein:

the at least one aspect of the command comprises whether the command is a write command, the write command comprising data to write to non-volatile memory in the memory device; and

the method further comprises responsive to determining that the command is a write command:

determining to execute the command without fetching the command from the submission queue; and

placing the no-operation entry in the submission queue as the command placeholder in the submission queue, wherein the no-operation entry does not include any data in the write command.

6. The method of claim 1 , further comprising:

responsive to determining to execute the command without fetching the command from the submission queue:

sending a completion message to the host device, the completion message indicative to the host device of completion of execution of the command;

wherein executing the command without fetching the command from the submission queue is performed after sending the completion message.

7. A memory device comprising:

memory comprising a submission queue and a completion queue;

a communication interface configured to communicate with a host device; and

a controller in communication with the memory and the communication interface, the controller configured to:

receive, via the communication interface from the host device, a command for execution;

analyze at least one aspect of the command;

determine, based on analyzing the at least one aspect of the command, whether to bypass execution of the command via the submission queue;

in response to determining to bypass execution of the command via the submission queue:

begin execution of the command without fetching the command from the submission queue; and

place a no-operation entry indicative of the command on the submission queue; and

in response to determining to not bypass execution of the command via the submission queue:

place an entry indicative of executing the command on the submission queue;

fetch the entry from the submission queue; and

responsive to fetching the entry, execute the command.

8. The memory device of claim 7 , wherein the controller is configured to:

analyze whether the command is a write command; and

responsive to determining that the command is a write command, bypass execution of the write command via the submission queue.

9. The memory device of claim 7 , wherein the controller is further configured to:

review the no-operation entry; and

responsive to the review, determine not to perform any operation.

10. The memory device of claim 7 , wherein the controller is further configured to, in response to determining to bypass execution of the command via the submission queue, send a completion message to the host device prior to beginning execution of the command, the completion message indicative to the host device of completion of the execution of the command.

11. A non-volatile memory device comprising:

a fabric communication interface;

a submission queue;

means for analyzing at least one aspect of a command received via the fabric communication interface;

means for determining, based on the analysis, whether to execute the command without fetching the command from the submission queue;

means for, responsive to determining to execute the command without fetching the command from the submission queue, placing a command placeholder other than the command into the submission queue, and executing the command without fetching the command from the submission queue; and

means for, responsive to determining to execute the command by fetching the command from the submission queue, placing the command into the submission queue, fetching the command from the submission queue, and thereafter executing the command.

12. The memory device of claim 7 , wherein the at least one aspect of the command comprises a type of the command.

13. The memory device of claim 12 , wherein the type of the command comprises a write command.

14. The memory device of claim 7 , wherein:

the command comprises a command capsule that includes an indication of a command operation and data on which to execute the command operation.

15. The memory device of claim 7 , wherein the controller is further configured to send a completion message to the host device responsive to determining that the command is a first predetermined type or is not a second predetermined type.

16. The memory device of claim 15 , wherein the first predetermined type comprises a write command.

17. The memory device of claim 15 , wherein the second predetermined type comprises a force unit access (FUA) command.

Assignments (10)
PARTIAL RELEASE OF SECURITY INTERESTS Recorded Apr 25, 2025
From: JPMORGAN CHASE BANK, N.A., AS AGENT
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 071382/0001 →
SECURITY AGREEMENT Recorded Apr 25, 2025
From: SANDISK TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 071050/0001 →
PATENT COLLATERAL AGREEMENT Recorded Aug 23, 2024
From: SANDISK TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS THE AGENT
Reel/Frame 068762/0494 →
CHANGE OF NAME Recorded Jun 27, 2024
From: SANDISK TECHNOLOGIES, INC.
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 067982/0032 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 29, 2024
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 067567/0682 →
PATENT COLLATERAL AGREEMENT - DDTL LOAN AGREEMENT Recorded Aug 21, 2023
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A.
Reel/Frame 067045/0156 →
PATENT COLLATERAL AGREEMENT - A&R LOAN AGREEMENT Recorded Aug 21, 2023
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A.
Reel/Frame 064715/0001 →
RELEASE OF SECURITY INTEREST AT REEL 052915 FRAME 0566 Recorded Feb 8, 2022
From: JPMORGAN CHASE BANK, N.A.
To: WESTERN DIGITAL TECHNOLOGIES, INC.
Reel/Frame 059127/0001 →
SECURITY INTEREST Recorded Feb 6, 2020
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS AGENT
Reel/Frame 052915/0566 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 17, 2017
From: BENISTY, SHAY
To: WESTERN DIGITAL TECHNOLOGIES, INC.
Reel/Frame 043023/0753 →
Continuity (2)
Continuation In Part 15468620 · Mar 24, 2017
Related Publication 20190018805A1 · Jan 17, 2019