IP Library Granted Patent US 10,734,084
Granted Patent B2
US 10,734,084 · App. 16/428,305 · Granted Aug 4, 2020

Scheme to reduce read disturb for high read intensive blocks in non-volatile memory

Inventors: Narayan Kuddannavar (Bangalore, IN); Swaroop Kaza (Milpitas, CA); Sainath Viswasarai (Bangalore, IN)
Assignee: Western Digital Technologies, Inc.
G11C16/3427G11C16/0483G11C16/10G11C16/26G11C16/3459H01L27/1157H01L27/11565H01L27/11582
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Quick Facts
Patent No.
US 10,734,084
App. No.
16/428,305
Granted
Aug 4, 2020
Kind
B2
Abstract

A non-volatile storage system comprises non-volatile memory cells arranged in physical blocks, and one or more control circuits in communication with the non-volatile memory cells. The one or more control circuits are configured to write data to a physical block of the non-volatile memory cells with a scheme to reduce read disturb if a logical block associated with the physical block has a read intensity greater than a threshold.

Claims (43)

1. An apparatus, comprising:

non-volatile memory cells arranged in physical blocks, wherein the physical blocks comprise data word lines connected to the memory cells, wherein each data word line is divided into a plurality of regions; and

one or more control circuits in communication with the non-volatile memory cells, the one or more control circuits configured to:

write data to a physical block of the non-volatile memory cells with a scheme to reduce read disturb if a logical block associated with the physical block has a read intensity greater than a threshold, including store dummy data in at least one region of the regions of a data word line in the physical block and store user data in at least one other region of the regions of the data word line in the physical block.

2. The apparatus of claim 1 , wherein the one or more control circuits are further configured to:

use a read scrub criterion for the physical block based on the read intensity of the logical block.

3. The apparatus of claim 1 , wherein the physical block is a first physical block, the logical block is a first logical block, and the one or more control circuits are further configured to:

write data to a second physical block of the non-volatile memory cells using a scheme that stores user/system data on all data memory cells in the second physical block if a second logical block associated with the second physical block has a read intensity less than the threshold.

4. The apparatus of claim 1 , wherein:

the non-volatile memory cells are arranged in columns in the physical block, the columns have a diameter that varies based on location of the non-volatile memory cells along the column; and

the one or more control circuits configured to write data with the scheme to reduce read disturb comprises the one or more control circuits configured to store dummy data in data memory cells at which the columns have the smallest diameter.

5. The apparatus of claim 1 , wherein:

the physical block comprises data word lines and a source line; and

the one or more control circuits configured to write data with the scheme to reduce read disturb comprises the one or more control circuits configured to store dummy data in data word lines closest to the source line.

6. The apparatus of claim 1 , wherein the one or more control circuits are further configured to:

store dummy data in data word lines on each side of the data word line in which the dummy data is stored in the at least one region of the regions and the user data is stored in at the least one of region the other regions.

7. The apparatus of claim 1 , wherein the one or more control circuits are further configured to:

store dummy data and user/system data on alternating data word lines in a second physical block if a second logical block associated with the second physical block has a read intensity less than the threshold.

8. The apparatus of claim 1 , wherein each region of the plurality of regions of each data word lines comprises a finger.

9. A method comprising:

performing a read scrub of a first physical block for which an associated first logical block has a read intensity above a threshold responsive to a first criterion to scrub being met with respect to the first physical block, wherein the first physical block comprises word lines, wherein each word line is divided into a plurality of fingers, performing the read scrub including writing the first physical block using a scheme that improves read disturb, writing the first physical block using a scheme that improves read disturb includes storing dummy data in at least one finger of the fingers of a data word line in the first physical block and storing user data on the other fingers of the data word line in the first physical block;

reading the first physical block without performing a read scrub responsive to the first criterion to scrub not being met;

performing a read scrub of a second physical block for which an associated second logical block has a read intensity below the threshold responsive to a second criterion to scrub being met with respect to the second physical block; and

reading the second physical block without performing a read scrub responsive to the second criterion to scrub not being met.

10. The method of claim 9 , wherein the first criterion is more relaxed than the second criterion.

11. The method of claim 9 , further comprising:

marking the second logical block as a high read intensive block responsive to a read intensity associated with the second logical block being greater than the threshold.

12. The method of claim 9 , wherein performing the read scrub of the second physical block further comprises writing the second physical block using a scheme that reduces read disturb responsive to a read intensity associated with the second logical block being greater than a threshold.

13. A non-volatile storage device comprising:

a three-dimensional array comprising physical blocks of non-volatile memory cells, the physical blocks comprising data word lines, wherein the non-volatile memory cells are arranged in columns in the physical blocks, the columns having a diameter that varies depending on location of the non-volatile memory cells along the columns; and

one or more control circuits in communication with the data word lines and the non-volatile memory cells, the one or more control circuits configured to:

store dummy data in first data word lines in a first physical block and store user/system data in second data word lines in the first physical block responsive to a read intensity of a first logical block associated with the first physical block being greater than a threshold, the first data word lines in the first physical block comprising a set of data word lines at which the columns have the smallest diameter; and

store user/system data in all data word lines in a second physical block responsive to a read intensity of a second logical block associated with the second physical block being less than the threshold.

14. The non-volatile storage device of claim 13 , wherein the one or more control circuits are further configured to:

perform a read scrub of the first physical block responsive to a first criterion to scrub being met with respect to the first physical block, including write the first physical block with a scheme that reduces read disturb; and

perform a read scrub of the second physical block responsive to a second criterion to scrub being met with respect to the second physical block, the second criterion is more strict than the first criterion.

15. The non-volatile storage device of claim 13 , wherein the first data word lines in the first physical block comprise a contiguous set of data word lines closest to a source line.

16. The non-volatile storage device of claim 13 , wherein each of the second data word lines in the first physical block has at least one of the first data word lines on each side each respective second data word line.

17. An apparatus, comprising:

non-volatile memory cells arranged in physical blocks, the non-volatile memory cells arranged in columns in the physical block, the columns having a diameter that varies based on location of the non-volatile memory cells along the column, the non-volatile memory cells including data memory cells; and

one or more control circuits in communication with the non-volatile memory cells, the one or more control circuits configured to:

write data to a physical block of the non-volatile memory cells with a scheme to reduce read disturb if a logical block associated with the physical block has a read intensity greater than a threshold, the one or more control circuits configured to write data with the scheme to reduce read disturb by storing dummy data in data memory cells at which the columns have the smallest diameter.

18. The apparatus of claim 17 , wherein the non-volatile memory cells are arranged in NAND strings in the physical block.

Assignments (10)
PARTIAL RELEASE OF SECURITY INTERESTS Recorded Apr 25, 2025
From: JPMORGAN CHASE BANK, N.A., AS AGENT
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 071382/0001 →
SECURITY AGREEMENT Recorded Apr 25, 2025
From: SANDISK TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 071050/0001 →
PATENT COLLATERAL AGREEMENT Recorded Aug 23, 2024
From: SANDISK TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS THE AGENT
Reel/Frame 068762/0494 →
CHANGE OF NAME Recorded Jun 27, 2024
From: SANDISK TECHNOLOGIES, INC.
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 067982/0032 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 29, 2024
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 067567/0682 →
PATENT COLLATERAL AGREEMENT - DDTL LOAN AGREEMENT Recorded Aug 21, 2023
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A.
Reel/Frame 067045/0156 →
PATENT COLLATERAL AGREEMENT - A&R LOAN AGREEMENT Recorded Aug 21, 2023
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A.
Reel/Frame 064715/0001 →
RELEASE OF SECURITY INTEREST AT REEL 052915 FRAME 0566 Recorded Feb 8, 2022
From: JPMORGAN CHASE BANK, N.A.
To: WESTERN DIGITAL TECHNOLOGIES, INC.
Reel/Frame 059127/0001 →
SECURITY INTEREST Recorded Feb 6, 2020
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS AGENT
Reel/Frame 052915/0566 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 18, 2019
From: KUDDANNAVAR, NARAYAN; KAZA, SWAROOP; VISWASARAI, SAINATH
To: WESTERN DIGITAL TECHNOLOGIES, INC.
Reel/Frame 050765/0175 →