Non-volatile memory with reverse state program
A memory system separately programs memory cells connected by a common word line to multiple sets of data states with the set of data states having higher threshold voltage data states being programmed before the set of data states having lower threshold voltage data states. The memory system also separately programs memory cells connected by an adjacent word line to the multiple sets of data states such that memory cells connected by the adjacent word line are programmed to higher data states after memory cells connected by the common word line are programmed to higher data states and prior to memory cells connected by the common word line are programmed to lower data states.
1. An apparatus, comprising:
a control circuit configured to connect to a plurality of non-volatile memory cells via a set of bit lines and a set of word lines, the control circuit is configured to:
complete programming to a first set of data states prior to starting programming to a second set of data states for non-volatile memory cells connected to a first word line of the set of word lines, the first set of data states are higher in threshold voltage than the second set of data states;
complete programming to the second set of data states prior to starting programming to a third set of data states for the non-volatile memory cells connected to the first word line, the second set of data states are higher in threshold voltage than the third set of data states; and
perform programming to the third set of data states for the non-volatile memory cells connected to the first word line.
2. The apparatus of claim 1 , wherein:
the control circuit is configured to apply first voltage pulses to the first word line to program to the first set of data states the non-volatile memory cells connected to the first word line, the first voltage pulses have an initial magnitude at a first voltage;
the control circuit is configured to apply second voltage pulses to the first word line to program to the second set of data states the non-volatile memory cells connected to the first word line, the second voltage pulses have an initial magnitude at a second voltage, the second voltage is less than the first voltage; and
the control circuit is configured to apply third voltage pulses to the first word line to program to the third set of data states the non-volatile memory cells connected to the first word line, the third voltage pulses have an initial magnitude at a third voltage, the third voltage is less than the second voltage.
3. The apparatus of claim 2 , wherein:
the control circuit is configured to apply a first pass voltage to an unselected word line while applying the first voltage pulses to the first word line to program to the first set of data states the non-volatile memory cells connected to the first word line;
the control circuit is configured to apply a second pass voltage to the unselected word line while applying the second voltage pulses to the first word line to program to the second set of data states the non-volatile memory cells connected to the first word line, the second pass voltage is lower than the first pass voltage; and
the control circuit is configured to apply a third pass voltage to the unselected word line while applying the third voltage pulses to the first word line to program to the third set of data states the non-volatile memory cells connected to the first word line, the third pass voltage is lower than the second pass voltage.
4. The apparatus of claim 1 , wherein:
the control circuit is configured to complete programming to the first set of data states prior to starting programming to the second set of data states for non-volatile memory cells connected to a second word line of the set of word lines after completing programming to the first set of data states for non-volatile memory cells connected to the first word line and prior to starting programming to the second set of data states for non-volatile memory cells connected to the first word line;
the control circuit is configured to perform programming to the second set of data states for non-volatile memory cells connected to the second word line after completing programming to the second set of data states for non-volatile memory cells connected to the first word line and prior to starting programming to the third set of data states for non-volatile memory cells connected to the first word line; and
the control circuit is configured to perform programming to the third set of data states for non-volatile memory cells connected to the second word line after completing programming to the third set of data states for non-volatile memory cells connected to the first word line.
5. The apparatus of claim 4 , wherein:
the first word line is adjacent the second word line.
6. The apparatus of claim 4 , wherein:
the first word line and the second word line are positioned in a same block.
7. The apparatus of claim 1 , wherein:
the control circuit is configured to complete programming to the first set of data states for non-volatile memory cells connected to a second word line of the set of word lines after completing programming to the first set of data states for non-volatile memory cells connected to the first word line and prior to starting programming to the second set of data states for non-volatile memory cells connected to the first word line;
the control circuit is configured to perform programming to the second set of data states for non-volatile memory cells connected to the second word line after completing programming to circuit is configured to complete programming to the first set of data states for non-volatile memory cells connected to a third word line of the set of word lines after completing programming to the second set of data states for non-volatile memory cells connected to the first word line;
the control the first set of data states for non-volatile memory cells connected to the third word line;
the control circuit is configured to perform programming to the second set of data states for non-volatile memory cells connected to the third word line after completing programming to the third set of data states for non-volatile memory cells connected to the first word line;
the control circuit is configured to perform programming to the third set of data states for non-volatile memory cells connected to the second word line after completing programming to the second set of data states for non-volatile memory cells connected to the third word line; and
the control circuit is configured to perform programming to the third set of data states for non-volatile memory cells connected to the third word line after completing programming to the third set of data states for non-volatile memory cells connected to the second word line.
8. The apparatus of claim 7 , wherein:
the second word line is adjacent the first word line and the third word line.
9. The apparatus of claim 7 , wherein:
the first word line, the second word line and the third word line are positioned in a same block.
10. The apparatus of claim 1 , wherein:
the control circuit is configured to complete programming to the first set of data states for non-volatile memory cells connected to a second word line of the set of word lines after completing programming to the first set of data states for non-volatile memory cells connected to the first word line and prior to starting programming to the second set of data states for non-volatile memory cells connected to the first word line;
the control circuit is configured to complete programming to the first set of data states for non-volatile memory cells connected to a third word line of the set of word lines after completing programming to the second set of data states for non-volatile memory cells connected to the first word line;
the control circuit is configured to perform programming to the second set of data states for non-volatile memory cells connected to the second word line after completing programming to the first set of data states for non-volatile memory cells connected to the third word line;
the control circuit is configured to complete programming to the first set of data states for non-volatile memory cells connected to a fourth word line of the set of word lines after completing programming to the third set of data states for non-volatile memory cells connected to the first word line;
the control circuit is configured to perform programming to the second set of data states for non-volatile memory cells connected to the third word line after completing programming to the first set of data states for non-volatile memory cells connected to the fourth word line;
the control circuit is configured to perform programming to the third set of data states for non-volatile memory cells connected to the second word line after completing programming to the second set of data states for non-volatile memory cells connected to the third word line;
the control circuit is configured to perform programming to the first set of data states for non-volatile memory cells connected to a fifth word line of the set of word lines after completing programming to the third set of data states for non-volatile memory cells connected to the second word line;
the control circuit is configured to complete programming to the second set of data states for non-volatile memory cells connected to the fourth word line after completing programming to the first set of data states for non-volatile memory cells connected to the fifth word line; and
the control circuit is configured to perform programming to the third set of data states for non-volatile memory cells connected to the third word line after completing programming to the second set of data states for non-volatile memory cells connected to the fourth word line.
11. The apparatus of claim 10 , wherein:
the first word line, the second word line, the third word line, the fourth word line and the fifth word line are arranged in a stack with the fourth word line above the fifth word line, the third word line above the fourth word line, the second word line above the third word line, the first word line above the second word line, the first word line is closest to a drain side of the plurality of non-volatile memory cells as compared to the second word line and the fifth word line is closest to a source side of the plurality of non-volatile memory cells as compared to the fourth word line.
12. The apparatus of claim 1 , wherein:
the control circuit is configured to program memory cells in an order starting with memory cells connected to a word line closest to a drain side of the plurality of non-volatile memory cells and ending with memory cells connected to a word line closest to a source side of the plurality of non-volatile memory cells.
13. The apparatus of claim 1 , wherein:
the control circuit is configured to program memory cells in an order starting with memory cells connected to a top word line and ending with memory cells connected to a bottom word line.
14. The apparatus of claim 1 , wherein:
the control circuit is configured to program memory cells in an order starting with memory cells connected to a bottom word line and ending with memory cells connected to a top word line.
15. The apparatus of claim 1 , wherein the control circuit is further configured to start programming to a fourth set of data states for the non-volatile memory cells connected to the first word line after completing programming to the third set of data states for the non-volatile memory cells connected to the first word line, the third set of data states are higher in threshold voltage than the fourth set of data states.
16. A method, comprising:
completing programming to a first set of data states prior to starting programming to a second set of data states for non-volatile memory cells connected to a first word line, the first set of data states are higher in threshold voltage than the second set of data states;
after completing programming to the first set of data states for non-volatile memory cells connected to the first word line and prior to starting programming to the second set of data states for non-volatile memory cells connected to the first word line, completing programming to the first set of data states prior to starting programming to the second set of data states for non-volatile memory cells connected to a second word line;
after completing programming to the first set of data states for non-volatile memory cells connected to the second word line and prior to starting programming to the second set of data states for the non-volatile memory cells connected to the second word line, performing programming to the second set of data states for non-volatile memory cells connected to the first word line; and
after completing programming to the second set of data states for non-volatile memory cells connected to the first word line, performing programming to the second set of data states for non-volatile memory cells connected to the second word line.
17. The method of claim 16 , further comprising:
after completing programming to the second set of data states for non-volatile memory cells connected to the second word line, performing programming to a third set of data states for non-volatile memory cells connected to the first word line, the second set of data states are higher in threshold voltage than the third set of data states; and
after completing programming to the third set of data states for non-volatile memory cells connected to the first word line, performing programming to the third set of data states for non-volatile memory cells connected to the second word line.
18. The method of claim 16 , further comprising:
programming to the first set of data states for non-volatile memory cells connected to a third word line of the set of word lines after completing programming to the second set of data states for non-volatile memory cells connected to the first word line and before programming to the second set of data states for non-volatile memory cells connected to the second word line;
after completing programming to the second set of data states for non-volatile memory cells connected to the second word line, performing programming to a third set of data states for non-volatile memory cells connected to the first word line, the second set of data states are higher in threshold voltage than the third set of data states' programming to the first set of data states for non-volatile memory cells connected to a fourth word line of the set of word lines after completing programming to the third set of data states for non-volatile memory cells connected to the first word line;
after completing programming to the first set of data states for non-volatile memory cells connected to the fourth word line, programming to the second set of data states for non-volatile memory cells connected to the third word line;
programming to the third set of data states for non-volatile memory cells connected to the second word line after completing programming to the second set of data states for non-volatile memory cells connected to the third word line;
programming to the first set of data states for non-volatile memory cells connected to a fifth word line of the set of word lines after completing programming to the third set of data states for non-volatile memory cells connected to the second word line;
programming to the second set of data states for non-volatile memory cells connected to the fourth word line after completing programming to the first set of data states for non-volatile memory cells connected to the fifth word line; and
programming to the third set of data states for non-volatile memory cells connected to the third word line after completing programming to the second set of data states for non-volatile memory cells connected to the fourth word line.
19. An apparatus, comprising:
a non-volatile memory structure comprising a first plurality of non-volatile memory cells connected to a first word line; and
a control circuit connected to the non-volatile memory structure, the control circuit is configured to:
apply first voltage pulses to the first word line to program the first plurality of non-volatile memory cells to a first set of data states prior to starting programming of the plurality of non-volatile memory cells to a second set of data states, the first set of data states are higher in threshold voltage than the second set of data states, the first voltage pulses have an initial magnitude at a first voltage;
apply second voltage pulses to the first word line to program the first plurality of non-volatile memory cells to the second set of data states prior to starting programming of the plurality of non-volatile memory cells to a third set of data states, the second set of data states are higher in threshold voltage than the third set of data states, the second voltage pulses have an initial magnitude at a second voltage, the second voltage is less than the first voltage; and
apply third voltage pulses to the first word line to program the first plurality of non-volatile memory cells to the third set of data states, the third voltage pulses have an initial magnitude at a third voltage, the third voltage is less than the second voltage.
20. The apparatus of claim 19 , wherein:
the non-volatile memory structure further comprises additional non-volatile memory cells connected to additional word lines, the additional non-volatile memory cells are positioned in NAND strings;
the control circuit is configured to apply a first pass voltage to the additional word lines while applying the first voltage pulses to the first word line to program the plurality of non-volatile memory cells to the first set of data states;
the control circuit is configured to apply a second pass voltage to the additional word lines while applying the second voltage pulses to the first word line to program the plurality of non-volatile memory cells to the second set of data states, the second pass voltage is lower than the first pass voltage; and
the control circuit is configured to apply a third pass voltage to the additional word lines while applying the third voltage pulses to the first word line to program the plurality of non-volatile memory cells to the first set of data states, the third pass voltage is lower than the second pass voltage.