Storage system and method for handling overheating of the storage system
A storage system and method for handling overheating of the storage system are disclosed. The method comprises determining whether a temperature sensed by a temperature sensor is above a first threshold temperature; and in response to determining that the temperature sensed by the temperature sensor is above the first threshold temperature, lowering a voltage supplied by a power supply to one or more components in the storage system comprising transistors, wherein lowering the voltage supplied to the one or more components reduces temperature by reducing leakage current of the transistors.
1. A method for handling overheating of a storage system, the method comprising:
performing the following in a storage system comprising a memory, a temperature sensor, a power supply, and a controller, wherein the controller comprises transistors:
executing first computer-readable program code by the controller to:
determine whether a temperature sensed by the temperature sensor is above a first threshold temperature by comparing the temperature sensed by the temperature sensor to the first threshold temperature; and
in response to determining that the temperature sensed by the temperature sensor is above the first threshold temperature, perform a thermal throttling operation to reduce a number of memory operations performed in the memory; and
executing second computer-readable program code by the controller to:
determine whether the thermal throttling operation was successful in lowering the temperature below the first threshold temperature by comparing a temperature sensed by the temperature sensor after performing the thermal throttling operation to the first threshold temperature; and
in response to determining that the thermal throttling operation was unsuccessful in lowering the temperature below the first threshold temperature, lower a voltage supplied by the power supply to the controller, wherein lowering the voltage supplied to the controller reduces temperature by reducing leakage current of the transistors in the controller.
2. The method of claim 1 further comprising lowering the voltage supplied by the power supply to another component that comprises transistors in the storage system until the temperature sensed by the temperature sensor is lower than the first threshold temperature.
3. The method of claim 1 , wherein the controller comprises one or more of the following: a random access memory and analog circuitry.
4. The method of claim 1 , wherein the memory comprises a three-dimensional memory.
5. The method of claim 1 , wherein the storage system is embedded in a host.
6. The method of claim 1 , wherein the storage system is removably connected to a host.
7. A storage system comprising:
a memory;
a temperature sensor;
a power supply;
a controller comprising transistors;
first computer-readable program code means for:
determining whether a temperature sensed by the temperature sensor is above a first threshold temperature by comparing the temperature sensed by the temperature sensor to the first threshold temperature; and
in response to determining that the temperature sensed by the temperature sensor is above the first threshold temperature, performing a thermal throttling operation to reducing a number of memory operations performed in the memory; and
second computer-readable program code means for:
determining whether the thermal throttling operation was successful in lowering the temperature below the first threshold temperature by comparing a temperature sensed by the temperature sensor after performing the thermal throttling operation to the first threshold temperature; and
in response to determining that the thermal throttling operation was unsuccessful in lowering the temperature below the first threshold temperature sensor, lowering a voltage supplied by the power supply to the controller, wherein lowering the voltage supplied to the controller reduces temperature by reducing leakage current of transistors in the controller.
8. The storage system of claim 7 further comprising:
means for reducing the voltage supplied to the memory to a voltage needed to execute a particular memory operation.
9. The storage system of claim 7 , wherein the controller comprises one or more of the following: a random access memory and analog circuitry.
10. The storage system of claim 7 , wherein the memory comprises a three-dimensional memory.
11. The storage system of claim 7 , wherein the storage system is embedded in a host.
12. The storage system of claim 7 , wherein the storage system is removably connected to a host.