IP Library Granted Patent US 10,996,862
Granted Patent B2
US 10,996,862 · App. 16/443,011 · Granted May 4, 2021

Adaptive read trim for second read data retention

Inventors: Phil Reusswig (San Jose, CA); Mohsen Purahmad (San Jose, CA); Sahil Sharma (San Jose, CA); Rohit Sehgal (San Jose, CA); Niles Yang (San Jose, CA)
Assignee: Western Digital Technologies, Inc.
G06F3/0616G06F3/0659G06F3/0679
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Quick Facts
Patent No.
US 10,996,862
App. No.
16/443,011
Granted
May 4, 2021
Kind
B2
Abstract

A data storage system performs operations including determining an endurance level of a block of memory cells; adjusting a read performance profile for the block of memory cells based on the determined endurance level; receiving a data read command specifying data to be read from a particular memory cell of the block of memory cells; and in response to the data read command, performing a read operation on the particular memory cell using the adjusted read performance profile.

Claims (59)

1. A data storage system, comprising a memory comprising a plurality of memory cells; and a controller in communication with the memory, the controller configured to:

determine an endurance level of a block of memory cells of the plurality of memory cells;

increase at least one of a read voltage ramp-up time, a read voltage stabilization time, a read voltage sense time, and/or a read voltage discharge time for the block of memory cells based on the determined endurance level;

receive a data read command specifying data to be read from a particular memory cell of the block of memory cells; and

in response to the data read command, perform a read operation on the particular memory cell using the increased read voltage ramp-up time, read voltage stabilization time, read voltage sense time, and/or read voltage discharge time.

2. The data storage system of claim 1 , wherein the controller being configured to determine the endurance level of the block of memory cells includes the controller being configured to:

increment an erase count associated with the block of memory cells each time the block of memory cells is erased; and

determine the endurance level based on the erase count.

3. The data storage system of claim 1 , wherein the controller being configured to determine the endurance level of the block of memory cells includes the controller being configured to:

compare an erase count associated with the block of memory cells with one or more erase count thresholds associated with beginning-of-life (BOL), middle-of-life (MOL), end-of-life (EOL), and beyond end-of-life (BEOL) classifications of the block of memory cells; and

determine the endurance level based on the comparison.

4. The data storage system of claim 1 , wherein the controller being configured to determine the endurance level of the block of memory cells includes the controller being configured to:

determine an erase count of one or more of the memory cells of the block of memory cells; and

determine the endurance level based on the erase count.

5. The data storage system of claim 1 , wherein the controller being configured to increase at least one of the read voltage ramp-up time, read voltage stabilization time, read voltage sense time, and/or read voltage discharge time for the block of memory cells based on the determined endurance level includes the controller being configured to:

determine whether the determined endurance level is associated with an EOL classification; and

in accordance with a determination that the determined endurance level is associated with the EOL classification, increase at least one of the read voltage ramp-up time, read voltage stabilization time, read voltage sense time, and/or read voltage discharge time for the block of memory cells.

6. The data storage system of claim 1 , wherein the controller being configured to increase at least one of the read voltage ramp-up time, read voltage stabilization time, read voltage sense time, and/or read voltage discharge time for the block of memory cells based on the determined endurance level includes the controller being configured to:

set at least one of the read voltage ramp-up time, read voltage stabilization time, read voltage sense time, and/or read voltage discharge time to a first value in accordance with a determination that the determined endurance level is associated with a MOL classification; and

increase at least one of the read voltage ramp-up time, read voltage stabilization time, read voltage sense time, and/or read voltage discharge time to a second value in accordance with a determination that the determined endurance level is associated with an EOL classification.

7. A data storage system, comprising a memory comprising a plurality of memory cells; and a controller in communication with the memory, the controller configured to:

in response to receiving a refresh read command, for each metablock of the plurality of memory cells:

determine an endurance level of the metablock;

compare the determined endurance level to a predetermined life cycle threshold;

in accordance with a determination that the determined endurance level exceeds the predetermined life cycle threshold:

determine whether the metablock includes any single level cell (SLC) memory cells; and

in accordance with a determination that the metablock does not include any SLC memory cells, perform a refresh read operation on the metablock; and

in accordance with a determination that the metablock includes an SLC memory cell, forgo performing the refresh read operation on the metablock, and perform a second refresh read operation on one or more blocks within the metablock which do not include any SLC memory cells.

8. The data storage system of claim 7 , wherein the controller is further configured to:

in accordance with a determination that the determined endurance level does not exceed the predetermined life cycle threshold, perform the refresh read operation on the metablock.

9. The data storage system of claim 7 , wherein the controller being configured to determine whether the metablock includes any SLC memory cells includes the controller being configured to search for the metablock in a listing of metablocks that include SLC memory cells.

10. The data storage system of claim 7 , wherein the controller being configured to perform the refresh read operation on the metablock includes the controller being configured to:

apply a pre-conditioning voltage to a plurality of word lines in the metablock in order to move the memory cells into, or keep the memory cells in, a second read condition.

11. A data storage system, comprising:

means for determining an endurance level of a block of memory cells;

means for increasing at least one of a read voltage ramp-up time, a read voltage stabilization time, a read voltage sense time, and/or a read voltage discharge time for the block of memory cells based on the determined endurance level;

means for receiving a data read command specifying data to be read from a particular memory cell of the block of memory cells; and

means for, in response to the data read command, performing a read operation on the particular memory cell using the increased read voltage ramp-up time, read voltage stabilization time, read voltage sense time, and/or read voltage discharge time.

12. A method for a data storage system, comprising a memory comprising a plurality of memory cells; and a controller in communication with the memory, the method comprising:

at the controller:

determining an endurance level of a block of memory cells of the plurality of memory cells;

increase at least one of a read voltage ramp-up time, a read voltage stabilization time, a read voltage sense time, and/or a read voltage discharge time for the block of memory cells based on the determined endurance level;

receiving a data read command specifying data to be read from a particular memory cell of the block of memory cells; and

in response to the data read command, performing a read operation on the particular memory cell using the increased read voltage ramp-up time, read voltage stabilization time, read voltage sense time, and/or read voltage discharge time.

13. The method of claim 12 , wherein determining the endurance level of the block of memory cells includes:

incrementing an erase count associated with the block of memory cells each time the block is erased; and

determining the endurance level based on the erase count.

14. The method of claim 12 , wherein determining the endurance level of the block of memory cells includes:

comparing an erase count associated with the block of memory cells with one or more erase count thresholds associated with beginning-of-life (BOL), middle-of-life (MOL), end-of-life (EOL), and beyond end-of-life (BEOL) classifications of the block of memory cells; and

determining the endurance level based on the comparison.

15. The method of claim 12 , wherein determining the endurance level of the block of memory cells includes:

determining an erase count of one or more of the memory cells of the block of memory cells; and

determining the endurance level based on the erase count.

16. The method of claim 12 , wherein increasing at least one of the read voltage ramp-up time, read voltage stabilization time, read voltage sense time, and/or read voltage discharge time for the block of memory cells based on the determined endurance level includes:

determining whether the determined endurance level is associated with an EOL classification; and

in accordance with a determination that the determined endurance level is associated with the EOL classification, increasing at least one of the read voltage ramp-up time, read voltage stabilization time, read voltage sense time, and/or read voltage discharge time for the block of memory cells.

17. The method of claim 12 , wherein increasing at least one of the read voltage ramp-up time, read voltage stabilization time, read voltage sense time, and/or read voltage discharge time for the block of memory cells based on the determined endurance level includes:

setting at least one of the read voltage ramp-up time, read voltage stabilization time, read voltage sense time, and/or read voltage discharge time to a first value in accordance with a determination that the determined endurance level is associated with a MOL classification; and

increasing at least one of the read voltage ramp-up time, read voltage stabilization time, read voltage sense time, and/or read voltage discharge time to a second value in accordance with a determination that the determined endurance level is associated with an EOL classification.

Assignments (10)
PARTIAL RELEASE OF SECURITY INTERESTS Recorded Apr 25, 2025
From: JPMORGAN CHASE BANK, N.A., AS AGENT
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 071382/0001 →
SECURITY AGREEMENT Recorded Apr 25, 2025
From: SANDISK TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 071050/0001 →
PATENT COLLATERAL AGREEMENT Recorded Aug 23, 2024
From: SANDISK TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS THE AGENT
Reel/Frame 068762/0494 →
CHANGE OF NAME Recorded Jun 27, 2024
From: SANDISK TECHNOLOGIES, INC.
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 067982/0032 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 29, 2024
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 067567/0682 →
PATENT COLLATERAL AGREEMENT - DDTL LOAN AGREEMENT Recorded Aug 21, 2023
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A.
Reel/Frame 067045/0156 →
PATENT COLLATERAL AGREEMENT - A&R LOAN AGREEMENT Recorded Aug 21, 2023
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A.
Reel/Frame 064715/0001 →
RELEASE OF SECURITY INTEREST AT REEL 052915 FRAME 0566 Recorded Feb 8, 2022
From: JPMORGAN CHASE BANK, N.A.
To: WESTERN DIGITAL TECHNOLOGIES, INC.
Reel/Frame 059127/0001 →
SECURITY INTEREST Recorded Feb 6, 2020
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS AGENT
Reel/Frame 052915/0566 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 15, 2019
From: REUSSWIG, PHIL; PURAHMAD, MOHSEN; SHARMA, SAHIL; SEHGAL, ROHIT; YANG, NILES
To: WESTERN DIGITAL TECHNOLOGIES, INC.
Reel/Frame 050063/0095 →