Dynamic calibration of frequency and power storage interface
A data storage device includes a controller and a memory. The controller includes a host interface and a memory interface. The controller receives inputs from the host, internal storage device inputs, device lifetime calculations, temperature readings and voltage readings. The controller then dynamically adjusts the frequency and voltage for the memory interface based upon the inputs received. As such, the memory interface operates are optimum conditions.
1. A data storage device, comprising:
one or more memory devices;
a comparator;
a plurality of latches coupled to the comparator; and
a controller coupled to the one or more memory devices, the controller comprising:
a host interface for coupling the data storage device to a host device;
a memory interface for coupling the one or more memory devices to the controller;
a voltage regulator;
an interface timing adjustment engine, wherein the interface timing adjustment engine is configured to adjust a frequency of a timing signal; and
one or more of:
an internal inputs monitor;
a host inputs module;
a device lifetime monitor;
a temperature sensor; and
a voltage sensor,
wherein the controller is configured to:
adjust one or more of the frequency of the timing signal or a voltage of the memory interface within a constraint and based upon information received from one or more of the internal inputs monitor, host inputs module, device lifetime monitor, temperature sensor, and voltage sensor;
determine values for maximum read and write frequencies;
determine values for minimum read and write frequencies;
determine maximum power for read and write voltages;
decrease frequency and increase voltage;
calibrate maximum frequency for read and write;
check for errors on one or more transmitted patterns over the memory interface;
determine a first data pattern at a first frequency;
determine a second data pattern at a second frequency;
determine, using the plurality of latches working in conjunction with the controller, whether the first data pattern equals the second data pattern;
increase the first frequency if the first data pattern equals the second data pattern; and
decrease the first frequency if the first data pattern does not equal the second data pattern.
2. The data storage device of claim 1 , wherein the controller is further configured to adjust the voltage of the memory interface within the constraint and based upon the information received from one or more of the internal inputs monitor, host inputs module, device lifetime monitor, temperature sensor and voltage sensor.
3. The data storage device of claim 1 , wherein the controller is further configured to receive one or more of the following: host device bus mode configuration, host device power class configuration, host device power specifications, and host device power high and low power configurations.
4. The data storage device of claim 1 , wherein the controller is further configured to receive one or more of the following: maximum LDPC decode time, memory device programming time, parallelism, number of FIMs, memory device state, memory device lifetime, memory device temperature, and memory interface voltage.
5. The data storage device of claim 1 , wherein the constraint includes that the frequency of the timing signal does not exceed a maximum frequency and a power of the memory interface does not exceed a maximum power.
6. A data storage device, comprising:
means to receive inputs regarding one or more of the following: internal device inputs, host inputs, device lifetime, temperature, and voltage means to adjust a frequency of a timing signal of the data storage device;
means to maximize, within a constraint, frequency of a timing signal of a memory interface of the data storage device, wherein the means to maximize is coupled to the means to receive inputs;
means to adjust, within the constraint, voltage of the memory interface, wherein the means to adjust voltage is coupled to the means to receive inputs;
means to determine values for maximum read and write frequencies;
means to determine values for minimum read and write frequencies;
means to determine maximum power for read and write voltages;
means to decrease frequency and increase voltage;
means to calibrate maximum frequency for read and write;
means to check for errors on one or more transmitted patterns over the memory interface;
means to determine a first data pattern at a first frequency;
means to determine a second data pattern at a second frequency;
a comparator;
means to determine whether the first pattern equals the second pattern;
means to increase the first frequency if the first data pattern equals the second data pattern; and
means to decrease the first frequency if the first data pattern does not equal the second data pattern.
7. The data storage device of claim 6 , further comprising means to receive one or more of the following: host device bus mode configuration, host device power class configuration, host device power specifications, host device power high and low power configurations, maximum LDPC decode time, memory device programming time, parallelism, number of FIMs, memory device state, memory device lifetime, memory device temperature, and memory interface voltage.
8. A data storage system, comprising:
a host device; and
a data storage device coupled to the host device, the data storage device including:
one or more memory devices;
a comparator;
a plurality of latches coupled to the comparator; and
a controller coupled to the one or more memory devices, the controller configured to:
receive inputs from one or more of:
internal device inputs;
host inputs;
a device lifetime;
a temperature; and
a voltage;
adjust a frequency of a timing signal using an interface timing adjustment engine;
adjust a maximize frequency of a timing signal of a memory interface of the data storage device and a voltage of the memory interface of the data storage device, the maximizing the frequency and adjusting the voltage being within a constraint and based upon the received inputs;
determine values for maximum read and write frequencies;
determine values for minimum read and write frequencies;
determine maximum power for read and write voltages;
decrease frequency and increase voltage;
calibrate maximum frequency for read and write;
check for errors on one or more transmitted patterns over the memory interface;
determine a first data pattern at a first frequency;
determine a second data pattern at a second frequency;
determine, using the plurality of latches working in conjunction with the controller, whether the first data pattern equals the second data pattern;
increase the first frequency if the first data pattern equals the second data pattern; and
decrease the first frequency if the first data pattern does not equal the second data pattern.
9. The data storage system of claim 8 , wherein, to determine the maximized frequency and adjusted voltage, the controller is further configured to increase frequency of the memory interface and simultaneously decrease voltage of the memory interface.
10. The data storage system of claim 8 , wherein, to determine the maximized frequency and adjusted voltage, the controller is further configured to decrease frequency of the memory interface and simultaneously increase voltage of the memory interface.
11. The data storage device of claim 8 , wherein the constraint includes that the frequency of the timing signal does not exceed a maximum frequency and a power of the memory interface does not exceed a maximum power.