Method for maximizing frequency while checking data integrity on a physical interface bus
A data storage device includes a controller and a memory. The controller includes a host interface and a memory interface. The controller performs a first operation on the memory through the memory interface at a first frequency associated with the host interface to determine a first data pattern. The controller performs a read operation on the memory through the memory interface at a second frequency to determine a second data pattern. The controller changes the first frequency by a predetermined amount until the first frequency is equal to a maximum operating frequency having an associated risk of a setup/hold violation that is below a predetermined probability.
1. A method comprising:
in a data storage device that includes a controller and a memory, wherein the controller includes a host interface and a memory interface,
performing, by the controller, a first operation on the memory through the memory interface at a first frequency associated with the host interface to determine a first data pattern;
performing a read operation on the memory through the memory interface at a second frequency to determine a second data pattern; and
changing the first frequency by a predetermined amount until the first frequency is equal to a maximum operating frequency having an associated risk of a setup/hold violation that is below a predetermined probability, wherein changing the first frequency comprises:
in response to the first pattern being equal to the second pattern,
increasing the first frequency by the predetermined amount.
2. The method of claim 1 , wherein the predetermined amount is based on a setup and hold time required by the read operation.
3. The method of claim 1 , wherein the predetermined amount is based on at least one of a change in operating voltage, operating temperature, or load of the host interface.
4. The method of claim 1 , further comprising terminating said changing when the first frequency is equal to the maximum operating frequency.
5. The method of claim 1 , wherein said changing occurs during an idle time of the host interface.
6. The method of claim 1 , wherein said changing occurs a predetermined amount of time after a completion of the controller servicing an interrupt.
7. The method of claim 1 , wherein the second frequency is a relaxed frequency that is lower than the maximum operating frequency.
8. The method of claim 1 , wherein the first operation is a write operation.
9. The method of claim 1 , wherein the first operation is a read operation.
10. A method comprising:
in a data storage device that includes a controller and a memory, wherein the controller includes a host interface and a memory interface,
performing, by the controller, a first operation on the memory through the memory interface at a first frequency associated with the host interface to determine a first data pattern;
performing a read operation on the memory through the memory interface at a second frequency to determine a second data pattern; and
+changing the first frequency by a predetermined amount until the first frequency is equal to a maximum operating frequency having an associated risk of a setup/hold violation that is below a predetermined probability, wherein changing the first frequency comprises:
in response to the first pattern being not equal to the second pattern,
decreasing the first frequency by the predetermined amount.
11. A method comprising:
in a data storage device that includes a controller and a memory, wherein the controller includes a host interface and a memory interface,
performing, by the controller, a first operation on the memory through the memory interface at a first frequency associated with the host interface to determine a first data pattern;
performing a read operation on the memory through the memory interface at a second frequency to determine a second data pattern; and
changing the first frequency by a predetermined amount until the first frequency is equal to a maximum operating frequency having an associated risk of a setup/hold violation that is below a predetermined probability, wherein the predetermined amount is based on a setup and hold time required by the read operation, wherein the first pattern is not equal to the second pattern and the setup and hold time determine a maximum frequency of operation of the host interface.
12. A data storage device, comprising:
a controller and a memory, wherein the controller includes a host interface and a memory interface,
the controller configured to perform a first operation on the memory through the memory interface at a first frequency of a timing circuit associated with the host interface to determine a first data pattern,
the controller further configured to perform a read operation on the memory through the memory interface at a second frequency of the timing circuit to determine a second data pattern; and
an interface timing adjustment engine configured to change the first frequency by a predetermined amount until the first frequency is equal to a maximum operating frequency having an associated risk of a setup/hold violation that is below a predetermined probability, further comprising a plurality of latches coupled to a comparator and working in conjunction with the controller to determine whether the first pattern equals the second pattern.
13. The data storage device of claim 12 , further comprising a timing device, wherein the controller is further configured to adjust a frequency of a timing signal associated with the host interface using the timing device to obtain the first frequency and the second frequency.
14. The data storage device of claim 13 , wherein the controller is further configured to generate a clock signal or a strobe signal, and wherein the timing signal includes the clock signal or the strobe signal.
15. The data storage device of claim 13 , further comprising a memory device, wherein the memory device is configured to generate a read enable signal, and wherein the timing signal includes the read enable signal.
16. A data storage device, comprising:
means for perform a first operation on a memory through a memory interface at a first frequency associated with a host interface to determine a first data pattern;
means for performing a read operation on the memory through the memory interface at a second frequency to determine a second data pattern;
means for changing the first frequency by a predetermined amount until the first frequency is equal to a maximum operating frequency having an associated risk of a setup/hold violation that is below a predetermined probability; and
means for determining, by a plurality of latches coupled to a comparator and working in conjunction with a controller, whether the first data pattern equals the second data pattern.
17. The data storage device of claim 16 , further comprising a data bus coupled between the host interface and the memory interface, the data bus configured to communicatively couple a controller of the data storage device to a non-volatile memory of the data storage device.
18. The data storage device of claim 16 , wherein the predetermined amount is based on a setup and hold time required by the read operation.
19. A method comprising:
in a data storage device that includes a controller and a memory, wherein the controller includes a host interface and a memory interface,
(a) writing, by the controller, a write data pattern to the memory through the memory interface at a first frequency associated with the host;
(b) reading a read data pattern from the memory through the memory interface at a lower frequency having an associated risk of a setup/hold violation that is below a predetermined probability;
(c) comparing the write data pattern to the read data pattern;
(d) either:
responsive to the write data pattern being equal to the read data pattern according to the comparison, increasing the first frequency by a predetermined amount; or
responsive to the write data pattern not being equal to the read data pattern according to the comparison, decreasing the first frequency by a predetermined amount; and
(e) repeating (a)-(c).
20. The method of claim 19 , further comprising:
executing (a)-(c) responsive to the controller entering an idle mode.
21. The method of claim 19 , further comprising:
waiting for an interrupt service routing to complete before executing (a)-(c).
22. A method comprising:
in a data storage device that includes a controller and a memory, wherein the controller includes a host interface and a memory interface,
(a) reading, by the controller, a first read data pattern from the memory through the memory interface at a low frequency having an associated risk of a setup/hold violation that is below a predetermined probability;
(b) reading a second read data pattern from the memory through the memory interface at a second frequency higher than the low frequency associated with the host;
(c) comparing the first read data pattern to the second read data pattern;
(d) either:
responsive to the first read data pattern being equal to the second read data pattern according to the comparison, increasing the second frequency by a predetermined amount; or
responsive to the first read data pattern not being equal to the second read data pattern according to the comparison, decreasing the second frequency by a predetermined amount; and
(e) repeating (a)-(c).
23. The method of claim 22 , further comprising:
executing (a)-(c) responsive to the controller entering an idle mode.
24. The method of claim 22 , further comprising:
waiting for an interrupt service routing to complete before executing (a)-(c).