Granted Patent B2

US 11,087,836 · App. 17/127,290 · Granted Aug 10, 2021

Inventors: Richard David Barndt (San Diego, CA); Bernardo Rub (Sudbury, MA); Mostafa El Gamal (Worcester, MA)

Assignee: Western Digital Technologies, Inc.

G11C11/5628G06F3/0679G06F11/1072G11C16/08G11C16/10G11C29/781G11C29/802G11C2211/5623

Abstract

Claims (56)

1. A method for programming a memory device, comprising:

executing a first encoding operation to generate a first set of encoded data;

performing a first programming operation to store the first set of encoded data into the memory device;

executing, based on the first set of encoded data, a second encoding operation to generate a second set of encoded data;

executing one or more decoding operations based on the first set of encoded data stored in the memory device and the second set of encoded data, to generate a set of decoded data;

executing, based on the set of decoded data, an encoding operation to generate a third set of encoded data; and

performing a second programming operation to store the third set of encoded data to the same memory device.

2. The method of claim 1 , wherein an amount of the second set of encoded data is less than an amount of the first set of encoded data.

3. The method of claim 1 , comprising:

prior to executing the one or more decoding operations, storing the second set of encoded data to a memory.

4. The method of claim 3 , wherein the memory is different from the memory device.

5. The method of claim 1 , wherein executing the one or more decoding operations comprises:

performing a first decoding operation, based on the first set of encoded data from the memory device and the second set of encoded data, to generate a first set of decoded data; and

performing a second decoding operation, based on the first set of decoded data, to generate the set of decoded data.

6. The method of claim 3 , wherein the second set of encoded data stored in the memory comprises additional parity bits for an error-correcting code, and the third set of encoded data comprises the same data as the first set of encoded data.

7. The method of claim 1 , wherein the first programming operation comprises a foggy programming operation, and wherein the second programming operation comprises a fine programming operation.

8. The method of claim 1 , wherein the one or more decoding operations comprise a foggy decoding operation and an error-correcting code decoding operation.

9. The method of claim 1 , comprising:

generating an additional page of data based on an XOR operation of a number of bits of data in each cell of the memory device.

10. The method of claim 1 , wherein the first set of encoded data comprises four pages of data, and the second set of encoded data comprises one page of data, and the set of decoded data comprises four pages of data.

11. The method of claim 1 , comprising:

receiving host data from a host device,

wherein executing the first encoding operation comprises generating, using an error-correcting code encoding scheme, the first set of encoded data based on the host data, and

wherein executing the second encoding operation comprises providing the first set of encoded data to a foggy encoder for performing a foggy encoding operation to generate the second set of encoded data.

12. A system, comprising:

a memory device; and

one or more controllers configured to cause:

executing a first encoding operation to generate a first set of encoded data;

performing a first programming operation to store the first set of encoded data into the memory device;

executing, based on the first set of encoded data, a second encoding operation to generate a second set of encoded data;

executing one or more decoding operations based on the first set of encoded data stored in the memory device and the second set of encoded data, to generate a set of decoded data;

executing, based on the set of decoded data, an encoding operation to generate a third set of encoded data; and

performing a second programming operation to store the third set of encoded data to the memory device.

13. The system of claim 12 , wherein an amount of the second set of encoded data is less than an amount of the first set of encoded data.

14. The system of claim 12 , wherein the one or more controllers are configured to cause:

prior to executing the one or more decoding operations, storing the second set of encoded data to a memory.

15. The system of claim 14 , wherein the memory is different from the memory device.

16. The system of claim 12 , wherein executing the one or more decoding operations comprises:

performing a first decoding operation, based on the first set of encoded data from the memory device and the second set of encoded data, to generate a first set of decoded data; and

performing a second decoding operation, based on the first set of decoded data, to generate the set of decoded data.

17. The system of claim 12 , wherein the one or more controllers are configured to cause:

receiving host data from a host device,

wherein executing the first encoding operation comprises generating, using an error-correcting code encoding scheme, the first set of encoded data based on the host data, and

wherein executing the second encoding operation comprises providing the first set of encoded data to a foggy encoder for performing a foggy encoding operation to generate the second set of encoded data.

18. An apparatus, comprising:

means for executing a first encoding operation to generate a first set of encoded data;

means for performing a first programming operation to store the first set of encoded data into a memory device;

means for executing, based on the first set of encoded data, a second encoding operation to generate a second set of encoded data;

means for executing one or more decoding operations based on the first set of encoded data stored in the memory device and the second set of encoded data, to generate a set of decoded data;

means for executing, based on the set of decoded data, an encoding operation to generate a third set of encoded data; and

means for performing a second programming operation to store the third set of encoded data to the memory device.

19. The apparatus of claim 18 , wherein an amount of the second set of encoded data is less than an amount of the first set of encoded data.

20. The apparatus of claim 19 , comprising:

means for receiving host data from a host device,

wherein the means for executing the first encoding operation comprises means for generating, using an error-correcting code encoding scheme, the first set of encoded data based on the host data, and

wherein the means for executing the second encoding operation comprises means for executing a foggy encoding operation to generate the second set of encoded data.

Assignments (10)

Continuity (3)