Error recovery handling
View Patent ↗A device that provides error recovery handling includes a processor that is configured to receive an error recovery request including error type information and a page address, where the error type information is mapped to a first error recovery technique. The processor may be configured to determine whether an error count associated with the flash memory circuit satisfies a first criterion and an error map associated with the flash memory circuit satisfies a second criterion, where the error count indicates a number of read errors that have occurred and the error map indicates blocks in which the read errors have occurred. The processor may be configured to utilize a second technique to attempt to recover data when the first and second criterions are satisfied, otherwise utilize the first technique to attempt to recover data, where the second technique is associated with recovering data stored in an offline flash memory circuit.
1. A computer-implemented method, comprising:
encountering an occurrence of an error with respect to a page of a flash memory, wherein the error is associated with an error type, and the error type is mapped to a first error recovery technique;
determining whether an error count associated with the flash memory fulfills an error count criterion, wherein the error count indicates a number of errors that have occurred on the flash memory;
determining whether an error map associated with the flash memory fulfills an error map criterion, wherein the error map indicates one or more areas of the flash memory in which the errors have occurred;
when the error count criterion and the error map criterion are fulfilled, employing a second error recovery technique in order to recover data stored in the page of the flash memory; and
when the error count criterion and the error map criterion are not fulfilled, employing the first error recovery technique in order to recover the data stored in the page of the flash memory.
2. The computer-implemented method of claim 1 , wherein the first error recovery technique is different than the second error recovery technique.
3. The computer-implemented method of claim 1 , wherein the second error recovery technique is associated with recovering data stored in an offline flash memory.
4. The computer-implemented method of claim 2 , further comprising:
setting, at predetermined intervals, the error count associated with the flash memory to zero; and
clearing, at the predetermined intervals, the error map associated with the flash memory.
5. The computer-implemented method of claim 1 , wherein the second error recovery technique comprises a redundant array of independent disks recovery technique.
6. The computer-implemented method of claim 1 , further comprising:
providing an indication that the flash memory is unavailable for error recovery when a likelihood that the data stored in the page of the flash memory is recoverable using the first error recovery technique does not meet a criterion.
7. A memory device, comprising:
one or more controllers,
wherein when an error is encountered with respect to a page of a flash memory, the error is associated with an error type, and the error type is mapped to a first error recovery technique, the one or more controllers are configured to cause:
determining whether an error count associated with the flash memory fulfills an error count criterion, wherein the error count indicates a number of errors that have occurred on the flash memory;
determining whether an error map associated with the flash memory fulfills an error map criterion, wherein the error map indicates one or more areas of the flash memory in which the errors have occurred;
when the error count criterion and the error map criterion are fulfilled, employing a second error recovery technique in order to recover data stored in the page of the flash memory; and
when the error count criterion and the error map criterion are not fulfilled, employing the first error recovery technique in order to recover the data stored in the page of the flash memory.
8. The memory device of claim 7 , wherein the second error recovery technique differs from the first error recovery technique.
9. The memory device of claim 7 , wherein the one or more controllers are configured to cause:
incrementing the error count associated with the flash memory prior to determining whether the error count fulfills the error count criterion.
10. The memory device of claim 9 , wherein the one or more controllers are configured to cause:
determining a block of the flash memory that includes the page of the flash memory; and
updating the error map associated with the flash memory to indicate that the errors have occurred in the block of the flash memory prior to determining whether the error map associated with the flash memory fulfills the error map criterion.
11. The memory device of claim 7 , wherein the one or more controllers are configured to cause:
employing the second error recovery technique to attempt to recover the data stored in the page of the flash memory when the error count criterion and the error map criterion are fulfilled irrespective of whether the flash memory is offline.
12. The memory device of claim 7 , wherein the one or more controllers are configured to cause:
determining whether the flash memory has been identified as potentially offline when the error count criterion and the error map criterion are fulfilled; and
identifying the flash memory as offline, when the error count criterion and the error map criterion are fulfilled and the flash memory has been identified as potentially offline; and
identifying the flash memory as potentially offline, when the error count criterion and the error map criterion are fulfilled and the flash memory has not been identified as potentially offline.
13. The memory device of claim 12 , wherein the one or more controllers are configured to cause:
determining whether the flash memory is identified as offline; and
employing the second error recovery technique to attempt to recover the page of the flash memory when the flash memory is identified as offline without determining whether the error count criterion and the error map criterion are fulfilled.
14. The memory device of claim 7 , wherein the one or more controllers are configured to cause:
resetting, on a periodic basis, the error count associated with the flash memory and the error map associated with the flash memory.
15. The memory device of claim 7 , further comprising one or more memories configured to store the error count associated with the flash memory and the error map associated with the flash memory, wherein the error map associated with the flash memory comprises a bitmap.
16. The memory device of claim 7 , wherein the one or more controllers are configured to cause:
determining whether the error count associated with the flash memory fulfills the error count criterion prior to determining whether the error map associated with the flash memory fulfills the error map criterion; and
when the error count fails to satisfy the error count criterion, bypassing determining whether the error map fulfills the error map criterion.
17. The memory device of claim 7 , wherein the one or more controllers are configured to cause:
when the error count associated with the flash memory exceeds a first threshold, determining that the error count associated with the flash memory fulfills the error count criterion; and
when the error map indicates that at least a number of one or more blocks of the flash memory in which the errors have occurred exceeds a second threshold, determining that the error map associated with the flash memory fulfills the error map criterion.
18. A system, comprising:
means for encountering an occurrence of an error with respect to a page of a flash memory, wherein the error is associated with an error type, and the error type is mapped to a first error recovery technique;
means for determining whether an error count associated with the flash memory fulfills an error count criterion, wherein the error count indicates a number of errors that have occurred on the flash memory;
means for determining whether an error map associated with the flash memory fulfills an error map criterion, wherein the error map indicates one or more areas of the flash memory in which the errors have occurred;
when the error count criterion and the error map criterion are fulfilled, means for employing a second error recovery technique in order to recover data stored in the page of the flash memory; and
when the error count criterion and the error map criterion are not fulfilled, means for employing the first error recovery technique in order to recover the data stored in the page of the flash memory.
19. The system of claim 18 , comprising:
means for incrementing the error count associated with the flash memory prior to determining whether the error count fulfills the error count criterion.
20. The system of claim 19 , comprising:
means for determining a block of the flash memory that includes the page of the flash memory; and
means for updating the error map associated with the flash memory to indicate that the errors have occurred in the block of the flash memory prior to determining whether the error map associated with the flash memory fulfills the error map criterion.