System for accelerated training of bit output timings
Aspects of a storage device including a controller memory, a die memory, and a plurality of accumulators corresponding to individual DQs are provided for accelerated DQ training and error detection. A controller stores first data in the controller memory, transfers second data to the die memory over an n-bit bus, and receives n bits of the second data from the die memory based on a DQS. The controller then compares n bits of the first data with n bits of the second data to produce n bit results received into respective accumulators, and the controller simultaneously updates different accumulators in response to bit mismatches. During DQ training, if an accumulator value meets a mismatch threshold, the controller modifies a DQS-DQ timing accordingly. During error detection of a read scrambled page, if an accumulator value does not meet an entropy threshold, the controller identifies an error associated with the page.
1. A storage device, comprising:
a controller memory and a die memory;
a controller configured to store first data in the controller memory, to transfer second data to the die memory over a bus having an n-bit width, and to compare n bits of the first data with n bits of the second data to produce n bit results; and
a plurality of accumulators each corresponding to one of the n bit results and including a first accumulator and a second accumulator;
wherein the controller is further configured to update the first accumulator in response to a first one of the n bit results indicating a first mismatch, and to simultaneously update the second accumulator in response to a second one of the n bit results indicating a second mismatch.
2. The storage device of claim 1 ,
wherein the controller is further configured to receive the n bits of the second data from the die memory based on a data strobe;
wherein the data strobe is offset with respect to a first one of the n bits of the second data by a first timing, and wherein the data strobe is offset with respect to a second one of the n bits of the second data by a second timing; and
wherein the controller is further configured to determine whether a first value of the first accumulator or a second value of the second accumulator meet a mismatch threshold, to modify the first timing when the first value meets the mismatch threshold, and to modify the second timing when the second value meets the mismatch threshold.
3. The storage device of claim 2 , wherein the controller is further configured to modify the first timing based on the first value and to modify the second timing based on the second value.
4. The storage device of claim 1 , wherein the second data transferred to the die memory comprises the first data.
5. The storage device of claim 1 , wherein the second data transferred to the die memory comprises a page from a non-volatile memory.
6. The storage device of claim 5 , wherein the controller is further configured to determine whether at least one of a first value of the first accumulator or a second value of the second accumulator does not meet an entropy threshold, and to identify an error associated with the page based on the determination.
7. The storage device of claim 1 , wherein the controller is further configured to compare the first data with the second data using one or more exclusive-or (XOR) gates or exclusive-nor (XNOR) gates.
8. A storage device, comprising:
a controller memory and a die memory;
a controller configured to store first data in the controller memory, to transfer second data to the die memory over a bus having an n-bit width, to receive n bits of the second data from the die memory based on a data strobe, and to compare n bits of the first data with the n bits of the second data to produce n bit results, wherein the data strobe is offset with respect to a first one of the n bits of the second data by a first timing, and wherein the data strobe is offset with respect to a second one of the n bits of the second data by a second timing; and
a plurality of accumulators each corresponding to one of the n bit results and including a first accumulator and a second accumulator, wherein the controller is further configured to update the first accumulator in response to a first one of the n bit results indicating a first mismatch, and to simultaneously update the second accumulator in response to a second one of the n bit results indicating a second mismatch;
wherein the controller is further configured to determine whether a first value of the first accumulator or a second value of the second accumulator meet a mismatch threshold, to modify the first timing when the first value meets the mismatch threshold, and to modify the second timing when the second value meets the mismatch threshold.
9. The storage device of claim 8 , wherein the controller is further configured to modify the first timing based on the first value and to modify the second timing based on the second value.
10. The storage device of claim 8 , wherein the second data transferred to the die memory comprises the first data.
11. The storage device of claim 8 , wherein the second data transferred to the die memory comprises a page from a non-volatile memory.
12. The storage device of claim 11 , wherein the controller is further configured to determine whether at least one of the first value of the first accumulator or the second value of the second accumulator does not meet an entropy threshold, and to identify an error associated with the page based on the determination.
13. The storage device of claim 8 , wherein the controller is further configured to compare the first data with the second data using one or more exclusive-or (XOR) gates or exclusive-nor (XNOR) gates.
14. A storage device, comprising:
a controller memory and a die memory;
a controller configured to store first data in the controller memory, to transfer second data to the die memory over a bus having an n-bit width, and to compare n bits of the first data with n bits of the second data to produce n bit results; and
a plurality of accumulators each corresponding to one of the n bit results and including a first accumulator and a second accumulator, wherein the controller is further configured to update the first accumulator in response to a first one of the n bit results indicating a first mismatch, and to simultaneously update the second accumulator in response to a second one of the n bit results indicating a second mismatch;
wherein the controller is further configured to determine whether at least one of a first value of the first accumulator or a second value of the second accumulator does not meet an entropy threshold, and to identify an error associated with the second data based on the determination.
15. The storage device of claim 14 ,
wherein the controller is further configured to receive the n bits of the second data from the die memory based on a data strobe;
wherein the data strobe is offset with respect to a first one of the n bits of the second data by a first timing, and wherein the data strobe is offset with respect to a second one of the n bits of the second data by a second timing; and
wherein the controller is further configured to determine whether the first value of the first accumulator or the second value of the second accumulator meet a mismatch threshold, to modify the first timing when the first value meets the mismatch threshold, and to modify the second timing when the second value meets the mismatch threshold.
16. The storage device of claim 15 , wherein the controller is further configured to modify the first timing based on the first value and to modify the second timing based on the second value.
17. The storage device of claim 14 , wherein the second data transferred to the die memory comprises the first data.
18. The storage device of claim 14 , wherein the second data transferred to the die memory comprises a page from a non-volatile memory.
19. The storage device of claim 14 , wherein the controller is further configured to compare the first data with the second data using one or more exclusive-or (XOR) gates.
20. The storage device of claim 14 , wherein the controller is further configured to compare the first data with the second data using one or more exclusive-nor (XNOR) gates.