IP Library Granted Patent US 11,714,750
Granted Patent B2
US 11,714,750 · App. 17/555,254 · Granted Aug 1, 2023

Data storage method and system with persistent memory and non-volatile memory

Inventors: Daniel Helmick (Broomfield, CO); Richard S. Lucky (Louisville, CO); Stephen Gold (Fort Collins, CO); Ryan R. Jones (Mesa, AZ)
Assignee: Western Digital Technologies, Inc.
G06F12/0623G06F12/0246G06F12/0653H10B99/00G06F12/0661G06F12/1072G06F2212/7203G06F2212/7208G06F2212/7209
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Quick Facts
Patent No.
US 11,714,750
App. No.
17/555,254
Granted
Aug 1, 2023
Kind
B2
Abstract

A storage system with a controller having a persistent memory interface to local memory is provided. The persistent memory can be used to store a logical-to-physical address table. A logical-to-physical address table manager, local to the controller or remote in a secondary controller, can be used to access the logical-to-physical address table. The manager can be configured to improve bandwidth and performance in the storage system.

Claims (57)

1. A data storage system, comprising:

persistent memory configured to store a logical-to-physical address table;

non-volatile memory;

a first controller coupled to the non-volatile memory, the first controller configured to receive multiple commands from a host system; and

a second controller coupled to the first controller and the persistent memory, the second controller configured to cause:

performing multiple changes to the logical-to-physical address table based on the multiple commands; and

transferring, in a single transfer, at least one of the multiple changes to the first controller for storage in the non-volatile memory without transferring each of the multiple changes one at a time and without performing multiple transfers to the first controller for the multiple changes,

wherein:

the data storage system is separate and different from the host system;

the persistent memory is not a dynamic random access memory;

the second controller is indirectly connected to the non-volatile memory via the first controller and is not directly connected to the non-volatile memory; and

the second controller is separate and different from the first controller.

2. The data storage system of claim 1 , wherein when at least a portion of the logical-to-physical address table in the persistent memory is valid, the data storage system is configured to cause declining to copy the at least a portion of the logical-to-physical address table from the non-volatile memory into the persistent memory.

3. The data storage system of claim 1 , wherein transferring the at least one of the multiple changes to the first controller comprises transferring only a most-recent change to the first controller.

4. The data storage system of claim 1 , wherein:

the second controller is configured to cause identifying duplicate and stale changes to the logical-to-physical address table; and

the at least one of the multiple changes being transferred to the first controller excludes the duplicate and stale changes.

5. The data storage system of claim 1 , wherein the second controller is configured to cause, prior to the transferring in the single transfer:

collecting all of the multiple changes; and

storing all of the multiple changes in the persistent memory without storing all of the multiple changes in the non-volatile memory.

6. The data storage system of claim 1 , wherein the second controller is configured to cause, prior to the transferring in the single transfer:

performing a compression operation on the at least one of the multiple changes.

7. The data storage system of claim 1 , wherein:

transferring, in the single transfer, the at least one of the multiple changes is caused to be performed during garbage collection, retention management or disturb management.

8. The data storage system of claim 2 , wherein the second controller is configured to cause:

in response to detecting power loss, causing the at least a portion of the logical-to-physical address table to remain in or to be written to the persistent memory for power off storage; and

in response to the host system re-booting after the power loss, verifying whether the at least a portion of the logical-to-physical address table in the persistent memory is valid.

9. A method for a data storage system, the method comprising:

receiving, by a first controller, multiple commands from a host system;

performing, by a second controller, multiple changes to a logical-to-physical address table in persistent memory based on the multiple commands; and

transferring, by the second controller, in a single transfer, at least one of the multiple changes to the first controller for storage in non-volatile memory without transferring each of the multiple changes one at a time and without performing multiple transfers to the first controller for the multiple changes,

wherein prior to the transferring in the single transfer, performing, by the second controller, a compression operation on the at least one of the multiple changes.

10. The method of claim 9 , wherein when at least a portion of the logical-to-physical address table in the persistent memory is valid, the method comprises declining to copy the at least a portion of the logical-to-physical address table from the non-volatile memory into the persistent memory.

11. The method of claim 9 , wherein:

the data storage system is separate and different from the host system; and

the data storage system comprises the second controller, the persistent memory and the non-volatile memory.

12. The method of claim 9 , wherein:

the persistent memory is not a dynamic random access memory;

the second controller is indirectly connected to the non-volatile memory via the first controller and is not directly connected to the non-volatile memory; and

the second controller is separate and different from the first controller.

13. The method of claim 9 , wherein transferring the at least one of the multiple changes to the first controller comprises transferring only most-recent one or more changes to the first controller.

14. The method of claim 9 , comprising:

identifying, by the second controller, duplicate and stale changes to the logical-to-physical address table,

wherein the at least one of the multiple changes being transferred to the first controller excludes the duplicate and stale changes.

15. The method of claim 9 , comprising, prior to the transferring in the single transfer:

collecting all of the multiple changes; and

storing all of the multiple changes in the persistent memory without storing all of the multiple changes in the non-volatile memory.

16. An apparatus, comprising:

means for receiving multiple commands from a host system;

means for performing multiple changes to a logical-to-physical address table in persistent memory based on the multiple commands;

means for transferring, in a single transfer, at least one of the multiple changes for storage in non-volatile memory without transferring each of the multiple changes one at a time and without performing multiple transfers for the multiple changes;

in response to detecting power loss, means for causing at least a portion of the logical-to-physical address table to remain in or to be written to the persistent memory for power off storage; and

in response to the host system re-booting after the power loss, means for verifying whether the at least a portion of the logical-to-physical address table in the persistent memory is valid.

17. The apparatus of claim 16 , comprising means for, when at least a portion of the logical-to-physical address table in the persistent memory is valid, declining to copy the at least a portion of the logical-to-physical address table from the non-volatile memory into the persistent memory.

18. The apparatus of claim 16 , comprising:

means for collecting all of the multiple changes; and

means for storing all of the multiple changes in the persistent memory without storing all of the multiple changes in the non-volatile memory, prior to transferring the at least one of the multiple changes.

Assignments (8)
PARTIAL RELEASE OF SECURITY INTERESTS Recorded Apr 25, 2025
From: JPMORGAN CHASE BANK, N.A., AS AGENT
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 071382/0001 →
SECURITY AGREEMENT Recorded Apr 25, 2025
From: SANDISK TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 071050/0001 →
PATENT COLLATERAL AGREEMENT Recorded Aug 23, 2024
From: SANDISK TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS THE AGENT
Reel/Frame 068762/0494 →
CHANGE OF NAME Recorded Jun 27, 2024
From: SANDISK TECHNOLOGIES, INC.
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 067982/0032 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 29, 2024
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 067567/0682 →
PATENT COLLATERAL AGREEMENT - DDTL LOAN AGREEMENT Recorded Aug 21, 2023
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A.
Reel/Frame 067045/0156 →
PATENT COLLATERAL AGREEMENT - A&R LOAN AGREEMENT Recorded Aug 21, 2023
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A.
Reel/Frame 064715/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 6, 2022
From: HELMICK, DANIEL; LUCKY, RICHARD S.; GOLD, STEPHEN; JONES, RYAN R.
To: WESTERN DIGITAL TECHNOLOGIES, INC.
Reel/Frame 058577/0515 →
Continuity (4)
Continuation 16711294 · Dec 11, 2019
Continuation 15628361 · Jun 20, 2017
Provisional Application 62518408 · Jun 12, 2017
Related Publication 20220114094A1 · Apr 14, 2022