IP Library Granted Patent US 10,521,343
Granted Patent B2
US 10,521,343 · App. 15/628,361 · Granted Dec 31, 2019

Storage system with a controller having a persistent memory interface to local memory

Inventors: Daniel Helmick (Broomfield, CO); Richard S. Lucky (Louisville, CO); Stephen Gold (Fort Collins, CO); Ryan R. Jones (Mesa, AZ)
Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
G06F12/0623G06F12/0653H01L27/1052G06F12/0661G06F12/1072
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Quick Facts
Patent No.
US 10,521,343
App. No.
15/628,361
Filed
Jun 20, 2017
Granted
Dec 31, 2019
Kind
B2
Art Unit
2136
USPC
711/5
Abstract

A storage system with a controller having a persistent memory interface to local memory is provided. The persistent memory can be used to store a logical-to-physical address table. A logical-to-physical address table manager, local to the controller or remote in a secondary controller, can be used to access the logical-to-physical address table. The manager can be configured to improve bandwidth and performance in the storage system.

Claims (50)

1. A data storage device, comprising:

a non-volatile memory;

a persistent memory configured to store a logical-to-physical address table;

a secondary controller coupled to the persistent memory and comprising a logical-to-physical address manager configured to access and update the logical-to-physical address table in the persistent memory; and

a primary controller comprising:

a host interface configured to communicate data and control signals with a host;

a memory interface configured to communicate command sequences with the non-volatile memory; and

a controller interface for communication with the secondary controller,

wherein the secondary controller is further configured to collect a group of changes to the logical-to-physical address table and send the group of changes to the primary controller via the controller interface for storage in the non-volatile memory,

wherein the secondary controller, the primary controller, the non-volatile memory and the persistent memory are housed within the data storage device that is different and separate from the host, and

wherein the persistent memory is different and separate from the non-volatile memory.

2. The data storage device of claim 1 , wherein the secondary controller is further configured to increase a queue depth of command sent to the persistent memory to match a bandwidth between the primary controller and a volatile memory.

3. The data storage device of claim 2 , wherein the secondary controller is further configured to collect a plurality of changes to the logical-to-physical address table and send only a sub-set of the changes to the primary controller via the controller interface for storage in the non-volatile memory.

4. The data storage device of claim 3 , wherein the sub-set only includes most-recent changes.

5. The data storage device of claim 1 , wherein the non-volatile memory comprises a three-dimensional memory.

6. The data storage device of claim 1 , wherein the data storage device is embedded in the host.

7. The data storage device of claim 1 , wherein the data storage device is removably connected to the host.

8. The data storage device of claim 1 , wherein the secondary controller is further configured to identify duplicate and stale changes to the logical-to-physical address table and send a group of changes excluding the duplicate and stale changes to the primary controller via the controller interface for storage in the non-volatile memory.

9. The data storage device of claim 1 , wherein:

in response to detecting power loss in the data storage device, the data storage device is configured to cause at least a portion of the logical-to-physical address table to remain in or to be written to the persistent memory for power off storage,

in response to re-booting the data storage device after the power loss, the data storage device is configured to verify whether the at least a portion of the logical-to-physical address table in the persistent memory is valid, and

when the at least a portion of the logical-to-physical address table in the persistent memory is valid, the data storage device is configured not to copy the at least a portion of the logical-to-physical address table from the non-volatile memory into the persistent memory.

10. The data storage device of claim 1 , wherein the secondary controller comprises one or more of the following: a data scrambler, an error correction code (ECC) encoder, and an ECC decoder.

11. The data storage device of claim 10 , wherein the secondary controller comprises one or more of the following: a degradation module and a wear leveling module.

12. A data storage device, comprising:

volatile memory;

a non-volatile memory;

a first controller for communication with the non-volatile memory via a memory interface, wherein the first controller comprises a host interface configured to communicate data and control signals with a host; and

a second controller for communication with the first controller via a controller interface of the first controller and the volatile memory, wherein the second controller comprises a remote logical-to-physical address manager configured to access and update a logical-to-physical address table copied from the non-volatile memory to the volatile memory,

wherein the second controller is further configured to collect a group of changes to the logical-to-physical address table and send the group of changes to the first controller via the controller interface for storage in the non-volatile memory,

wherein the first controller, the second controller, the non-volatile memory and the volatile memory are housed within the data storage device that is different and separate from the host, and

wherein the volatile memory is different and separate from the non-volatile memory.

13. The data storage device of claim 12 , wherein the second controller is further configured to collect a plurality of changes to the logical-to-physical address table and send only a sub-set of the changes to the first controller via the controller interface for storage in the non-volatile memory.

14. The data storage device of claim 13 , wherein the sub-set only include most-recent changes.

15. The data storage device of claim 12 , wherein the non-volatile memory comprises a three-dimensional memory.

16. The data storage device of claim 12 , wherein the data storage device is embedded in the host.

17. The data storage device of claim 12 , wherein the data storage device is removably connected to the host.

18. A data storage device comprising:

a non-volatile memory;

a persistent memory;

means for interacting with a logical-to-physical address table stored in the persistent memory; and

a primary controller comprising:

a host interface configured to communicate data and control signals with a host;

a memory interface configured to communicate command sequences with the non-volatile memory; and

a controller interface for communication with the means for interacting,

wherein the means for interacting comprises means for collecting a group of changes to the logical-to-physical address table and sending the group of changes to the primary controller via the controller interface for storage in the non-volatile memory,

wherein the primary controller, the means for interacting, the non-volatile memory and the persistent memory are housed within the data storage device that is different and separate from the host, and

wherein the persistent memory is different and separate from the non-volatile memory.

19. The data storage device of claim 18 , wherein the means for interacting comprises a secondary controller.

20. The data storage device of claim 18 , wherein the data storage device is removably connected to the host.

Assignments (10)
PARTIAL RELEASE OF SECURITY INTERESTS Recorded Apr 25, 2025
From: JPMORGAN CHASE BANK, N.A., AS AGENT
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 071382/0001 →
SECURITY AGREEMENT Recorded Apr 25, 2025
From: SANDISK TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 071050/0001 →
PATENT COLLATERAL AGREEMENT Recorded Aug 23, 2024
From: SANDISK TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS THE AGENT
Reel/Frame 068762/0494 →
CHANGE OF NAME Recorded Jun 27, 2024
From: SANDISK TECHNOLOGIES, INC.
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 067982/0032 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 29, 2024
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 067567/0682 →
PATENT COLLATERAL AGREEMENT - DDTL LOAN AGREEMENT Recorded Aug 21, 2023
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A.
Reel/Frame 067045/0156 →
PATENT COLLATERAL AGREEMENT - A&R LOAN AGREEMENT Recorded Aug 21, 2023
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A.
Reel/Frame 064715/0001 →
RELEASE OF SECURITY INTEREST AT REEL 052915 FRAME 0566 Recorded Feb 8, 2022
From: JPMORGAN CHASE BANK, N.A.
To: WESTERN DIGITAL TECHNOLOGIES, INC.
Reel/Frame 059127/0001 →
SECURITY INTEREST Recorded Feb 6, 2020
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS AGENT
Reel/Frame 052915/0566 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 20, 2017
From: HELMICK, DANIEL; LUCKY, RICHARD S.; GOLD, STEPHEN; JONES, RYAN R.
To: WESTERN DIGITAL TECHNOLOGIES, INC.
Reel/Frame 042761/0317 →