IP Library Granted Patent US 10,204,693
Granted Patent B2
US 10,204,693 · App. 15/396,547 · Granted Feb 12, 2019

Retiring computer memory blocks

Inventors: Ming-Yu Tai (Irvine, CA); Yun-Tzuo Lai (Irvine, CA); Yung-Li Ji (Santa Ana, CA); Haining Liu (Irvine, CA)
Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
G11C16/3495G06F3/0619G06F3/0655G06F3/0688G06F11/076G06F12/02G06F12/0246G06F12/0253G11C16/349G06F2212/1036G06F2212/1044G06F2212/7211
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Quick Facts
Patent No.
US 10,204,693
App. No.
15/396,547
Granted
Feb 12, 2019
Kind
B2
Abstract

A method, system, and apparatus are provided for retiring computer memory blocks. Two overall schemes are provided for separating poorly functioning blocks from normally functioning blocks. In a first scheme, after data relocation is finished, firmware remembers the old physical memory block. As soon as the system writes to the old physical memory block with new data, firmware issues a read again and receives back a count of error bits. If the returned error bits are still high, then the system identifies the block as being weak and retires the block. In a second scheme, firmware tracks statistics for data relocates, block reads, activity timers, among other statistics. If some blocks have abnormal activities (e.g., too many data relocates, too many reads, etc.), then the system may identify the block as being weak and may retire the physical memory block.

Claims (66)

1. A method for retiring computer memory blocks in a memory apparatus, the method comprising:

receiving a read request from a processor in a host computer;

performing a read on a memory block in the memory apparatus that are block writeable;

receiving a count of error bits for the memory block;

determining whether the count of error bits is above an acceptability threshold for a bit error rate; and

if the count of error bits is above the acceptability threshold for the bit error rate, then

determining if the memory block is weak;

relocating data stored in the memory block to another memory block;

performing a post-relocate check on the memory block when the memory block is determined to not be weak; and

retiring the memory block from the memory apparatus so that it is no longer utilized to store data based on the post-relocate check.

2. The method of claim 1 , wherein

the read request is directed toward a page of the memory block in the memory apparatus.

3. The method of claim 1 , wherein

the memory apparatus includes flash memory having one or more integrated circuits with electrically erasable programmable read only memory cells.

4. The method of claim 1 , wherein

the count of error bits is included in an error bit code associated with the memory block in the memory apparatus.

5. The method of claim 1 , wherein the post-relocate check comprises:

calculating a number of data relocates have occurred from the memory block;

determining if the number of relocates is above an acceptability threshold for data relocates; and

if the number of relocates is above the acceptability threshold for data relocates, then

retiring the memory block in the memory apparatus.

6. The method of claim 1 , further comprising:

calculating a number of reads that have occurred from the memory block;

determining if the number of reads is above an acceptability threshold for reads; and

if the number of reads is above the acceptability threshold for reads, then

performing background scan operations to determine if the memory block is to be retired.

7. The method of claim 1 , further comprising:

calculating the duration that the memory block has been powered on;

determining if the duration is greater than a predetermined time period;

if the duration is greater than the predetermined time period, then

performing background scan operations to determine if the memory block is to be retired.

8. The method of claim 1 , wherein the retiring of the memory block comprises:

moving a pointer to the memory block from a normal list to a retired list.

9. A non-transitory computer readable medium carrying one or more instructions for retiring memory blocks in a memory apparatus, wherein the one or more instructions, when executed by one or more processors, cause the one or more processors to perform steps of:

receiving a read request from a processor in a host computer;

performing a read on a memory block in the memory apparatus that are block writeable;

receiving a count of error bits for the memory block;

determining whether the count of error bits is above an acceptability threshold for a bit error rate; and

if the count of error bits is above the acceptability threshold for the bit error rate, then

determining if the memory block is weak,

relocating data stored in the memory block to another memory block,

performing a post-relocate check on the memory block when the memory block is determined to not be weak, and

retiring the memory block from the memory apparatus so that it is no longer utilized to store data based on the post-relocate check.

10. The non-transitory computer readable medium of claim 9 , wherein

the read request is directed toward a page of the memory block in the memory apparatus.

11. The non-transitory computer readable medium of claim 9 , wherein

the memory apparatus includes flash memory having one or more integrated circuits with electrically erasable programmable read only memory cells.

12. The non-transitory computer readable medium of claim 9 , wherein

the count of error bits is included in an error bit code associated with the memory block in the memory apparatus.

13. The non-transitory computer readable medium of claim 9 , wherein the post-relocate check causes the one or more processors to perform steps of:

calculating a number of data relocates have occurred from the memory block;

determining if the number of relocates is above an acceptability threshold for data relocates; and

if the number of relocates is above the acceptability threshold for data relocates, then

retiring the memory block in the memory apparatus.

14. The non-transitory computer readable medium of claim 9 , wherein the one or more instructions cause the one or more processors to perform steps of:

calculating a number of reads that have occurred from the memory block;

determining if the number of reads is above an acceptability threshold for reads; and

if the number of reads is above the acceptability threshold for reads, then

performing background scan operations to determine if the memory block is to be retired.

15. The non-transitory computer readable medium of claim 9 , wherein the one or more instructions cause the one or more processors to perform steps of:

calculating the duration that the memory block has been powered on;

determining if the duration is greater than a predetermined time period;

if the duration is greater than the predetermined time period, then

performing background scan operations to determine if the memory block is to be retired.

16. The non-transitory computer readable medium of claim 9 , wherein the retiring of the memory block comprises:

moving a pointer to the memory block from a normal list to a retired list.

Assignments (10)
PARTIAL RELEASE OF SECURITY INTERESTS Recorded Apr 25, 2025
From: JPMORGAN CHASE BANK, N.A., AS AGENT
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 071382/0001 →
SECURITY AGREEMENT Recorded Apr 25, 2025
From: SANDISK TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 071050/0001 →
PATENT COLLATERAL AGREEMENT Recorded Aug 23, 2024
From: SANDISK TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS THE AGENT
Reel/Frame 068762/0494 →
CHANGE OF NAME Recorded Jun 27, 2024
From: SANDISK TECHNOLOGIES, INC.
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 067982/0032 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 29, 2024
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 067567/0682 →
PATENT COLLATERAL AGREEMENT - DDTL LOAN AGREEMENT Recorded Aug 21, 2023
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A.
Reel/Frame 067045/0156 →
PATENT COLLATERAL AGREEMENT - A&R LOAN AGREEMENT Recorded Aug 21, 2023
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A.
Reel/Frame 064715/0001 →
RELEASE OF SECURITY INTEREST AT REEL 052915 FRAME 0566 Recorded Feb 8, 2022
From: JPMORGAN CHASE BANK, N.A.
To: WESTERN DIGITAL TECHNOLOGIES, INC.
Reel/Frame 059127/0001 →
SECURITY INTEREST Recorded Feb 6, 2020
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS AGENT
Reel/Frame 052915/0566 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 1, 2017
From: TAI, MING-YU; LIU, HAINING; LAI, YUN-TZUO; JI, YUNG-LI
To: WESTERN DIGITAL TECHNOLOGIES, INC.
Reel/Frame 041151/0005 →
Continuity (1)
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