Multi-state programming for memory devices
Storage device programming methods, systems and media are described. A method may include encoding data to generate an encoded set of data. A first programming operation may write the encoded set of data to a memory device. The method includes encoding, using a second encoding operation based on the data, to generate a second set of encoded data. The second set of encoded data is stored to a cache. A first decoding operation is performed, based on the second set of encoded data and the encoded set of data, to generate a decoded set of data. A second decoding operation is performed to generate a second decoded set of data. The second decoded set of data is encoded to generate a third set of encoded data. The method includes performing a second programming operation to write the third set of encoded data to the memory device.
1. A data storage system, comprising:
memory; and
one or more controllers configured to cause:
encoding data to generate a first set of encoded data;
writing, during a first phase, the first set of encoded data to the memory;
encoding the first set of encoded data to generate a second set of encoded data;
receiving the first set of encoded data from the memory and the second set of encoded data;
performing one or more decoding operations, based on the received first and second sets of encoded data, to generate a set of decoded data;
encoding the set of decoded data to generate a third set of encoded data; and
writing, during a second phase, the third set of encoded data to the same memory.
2. The data storage system of claim 1 , wherein:
encoding the data comprises encoding the data using a first encoding operation; and
encoding the first set of encoded data comprises encoding the first set of encoded data using a second encoding operation that is different from the first encoding operation.
3. The data storage system of claim 1 , wherein an amount of the second set of encoded data is less than an amount of the first set of encoded data.
4. The data storage system of claim 1 , wherein performing the one or more decoding operations comprises:
performing a first decoding operation, based on the first set of encoded data from the memory and the second set of encoded data, to produce a first set of decoded data; and
performing a second decoding operation, based on the first set of decoded data, to generate the set of decoded data.
5. The data storage system of claim 1 , wherein:
writing during the first phase comprises a foggy programming operation; and
writing during the second phase comprises a fine programming operation.
6. The data storage system of claim 1 , wherein the one or more decoding operations comprise a foggy decoding operation and an error-correcting code decoding operation.
7. The data storage system of claim 1 , wherein:
the one or more controllers are configured to receive host data from a host device;
the data comprises the host data;
encoding the data comprises generating, using an error-correcting code encoding scheme, a set of encoded pages based on the host data, wherein the first set of encoded data comprises the set of encoded pages; and
encoding the first set of encoded data comprises performing a foggy encoding operation on the set of encoded pages.
8. The data storage system of claim 1 , wherein the one or more controllers are configured to cause: generating an additional page of data based on an XOR operation of a number of bits of data in each cell of the memory.
9. The data storage system of claim 1 , wherein the first set of encoded data comprises four pages of data, and the second set of encoded data comprises one page of data, and the set of decoded data comprises four pages of data.
10. The data storage system of claim 1 , wherein the one or more controllers are configured to cause: prior to performing the one or more decoding operations, storing the second set of encoded data to a second memory that is different from the memory.
11. The data storage system of claim 10 , wherein:
the second set of encoded data stored in the second memory comprises additional parity bits for an error-correcting code; and
the third set of encoded data comprises the same data as the first set of encoded data.
12. A method for a data storage system, the method comprising:
encoding data to generate a first set of encoded data;
writing, during a first phase, the first set of encoded data to memory;
encoding the first set of encoded data to generate a second set of encoded data;
receiving the first set of encoded data from the memory and the second set of encoded data;
performing one or more decoding operations, based on the received first and second sets of encoded data, to generate a set of decoded data;
encoding the set of decoded data to generate a third set of encoded data; and
writing, during a second phase, the third set of encoded data to the same memory.
13. The method of claim 12 , wherein:
encoding the data comprises encoding the data using a first encoding operation; and
encoding the first set of encoded data comprises encoding the first set of encoded data using a second encoding operation that is different from the first encoding operation.
14. The method of claim 12 , wherein an amount of the second set of encoded data is less than an amount of the first set of encoded data.
15. The method of claim 12 , wherein performing the one or more decoding operations comprises:
performing a first decoding operation, based on the first set of encoded data from the memory and the second set of encoded data, to produce a first set of decoded data; and
performing a second decoding operation, based on the first set of decoded data, to generate the set of decoded data.
16. The method of claim 12 , wherein:
writing during the first phase comprises a foggy programming operation; and
writing during the second phase comprises a fine programming operation.
17. The method of claim 12 , comprising: prior to performing the one or more decoding operations, storing the second set of encoded data to a second memory that is different from the memory.
18. The method of claim 17 , wherein:
the second set of encoded data stored in the second memory comprises additional parity bits for an error-correcting code; and
the third set of encoded data comprises the same data as the first set of encoded data.
19. An apparatus, comprising:
means for encoding data to generate a first set of encoded data;
means for writing, during a first phase, the first set of encoded data to memory;
means for encoding the first set of encoded data to generate a second set of encoded data;
means for performing one or more decoding operations, based on the first set of encoded data from the memory and the second set of encoded data, to generate a set of decoded data;
means for encoding the set of decoded data to generate a third set of encoded data; and
writing, during a second phase, the third set of encoded data to the same memory.
20. The apparatus of claim 19 , wherein:
the means for encoding data comprises means for encoding the data using a first encoding operation; and
the means for encoding the first set of encoded data comprises means for encoding the first set of encoded data using a second encoding operation that is different from the first encoding operation.