IP Library Granted Patent US 11,301,153
Granted Patent B2
US 11,301,153 · App. 16/899,580 · Granted Apr 12, 2022

High-throughput out-of-order cipher text stealing

Inventors: Amir Segev (Meitar, IL); Yuval Yoskovits (Beer Sheva, IL); Shay Benisty (Beer Sheva, IL)
Assignee: Western Digital Technologies, Inc.
G06F3/064G06F3/0619G06F3/0622G06F3/0656G06F3/0659G06F3/0673G06F21/602G06F21/78
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Quick Facts
Patent No.
US 11,301,153
App. No.
16/899,580
Granted
Apr 12, 2022
Kind
B2
Abstract

A method and device for out-of-order cryptographic processing to eliminate or ameliorate data dependency stalls, in the cryptographic pipeline of a data storage device, resulting from the application of cipher text stealing. A cryptographic processing pipeline performs the steps of: a) cryptographically process a penultimate data block, to produce a penultimate processed data block, and store a portion of the penultimate processed data block in the memory store; b) cryptographically process at least one leading data block, to produce at least one processed leading data block; and c) cryptographically process a concatenation of a last data block and the portion of the penultimate processed data block, to produce a last processed data block, wherein the cryptographic processing pipeline starts to perform step b) before completing step a).

Claims (76)

1. A data storage device comprising:

a non-transitory storage medium; and

a cryptographic processing unit, integrated with the data storage device, and configured to:

receive a first portion of a data object;

receive a second portion of the data object, wherein:

the first portion includes a penultimate data block; and

the second portion includes at least one leading data block of one or more leading data blocks; and

the first portion is received before the second portion; and

perform cryptographic processing of the data object to produce a processed data object, wherein:

the data object comprises a sequence of data blocks, including:

the one or more leading data blocks;

the penultimate data block; and

a last data block;

the cryptographic processing unit comprises:

a memory store;

a cryptographic processing pipeline; and

a pipeline controller;

the pipeline controller is configured to control the cryptographic processing pipeline to perform the steps of:

a) cryptographically process the penultimate data block, to produce a penultimate processed data block, and store a portion of the penultimate processed data block in the memory store;

b) cryptographically process at least one of the one or more leading data blocks, to produce one or more processed leading data blocks; and

c) cryptographically process a concatenation of the last data block and the portion of the penultimate processed data block, to produce a last processed data block; and

the pipeline controller is further configured to control the cryptographic processing pipeline to start to perform step b) before the cryptographic processing pipeline completes step a).

2. The data storage device of claim 1 , wherein performing cryptographic processing comprises performing encryption.

3. The data storage device of claim 1 , wherein performing cryptographic processing comprises performing decryption.

4. The data storage device of claim 1 , wherein:

each leading data block has a size equal to a set block size;

the penultimate data block has a size equal to a set block size; and

the last data block has a size less than the set block size.

5. The data storage device of claim 1 , wherein the cryptographic processing pipeline comprises a plurality of pipeline stages comprising, at least, a first stage and a second stage.

6. The data storage device of claim 5 , wherein the pipeline controller is further configured to control the first stage of the cryptographic processing pipeline to start to perform step b) while the second stage of the cryptographic processing pipeline continues to perform step a).

7. The data storage device of claim 1 , wherein the cryptographic processing pipeline is clocked by a clock signal.

8. The data storage device of claim 7 , wherein the cryptographic processing pipeline stores the portion of the penultimate processed data block in the memory store at least one clock cycle of the clock signal before an input stage of the cryptographic processing pipeline starts to perform step c).

9. The data storage device of claim 1 , wherein the cryptographic processing pipeline processes all of the one or more leading data blocks in step b).

10. The data storage device of claim 1 , further comprising:

an output buffer configured to store the penultimate processed data block; and

an output port configured to:

output processed data blocks from the cryptographic processing unit, and

output the last processed data block before outputting the penultimate processed data block, stored in the output buffer.

11. The data storage device of claim 1 , further comprising an input port in communication with a source of data blocks of the data object, wherein the cryptographic processing unit is configured to request and receive data blocks of the data object from the source via the input port.

12. The data storage device of claim 11 , wherein the cryptographic processing unit is further configured to:

request the first portion of the data object from the source via the input port; and

then request the second portion of the data object from the source via the input port.

13. The data storage device of claim 1 , wherein step a) comprises determining a tweak value associated with the penultimate data block.

14. The data storage device of claim 13 , wherein the cryptographic processing unit is configured to determine the tweak value associated with the penultimate data block before performing step a).

15. The data storage device of claim 1 , wherein the cryptographic processing unit is configured to calculate a tweak value for each data block in the sequence of data blocks.

16. The data storage device of claim 1 , wherein the cryptographic processing unit is configured to perform encryption in accordance with an XTS-AES encryption algorithm.

17. The data storage device of claim 1 , wherein the cryptographic processing unit is configured to perform decryption in accordance with an XTS-AES decryption algorithm.

18. A method for performing cryptographic processing of a data object to produce a processed data object, wherein:

the data object comprises a sequence of data blocks, including,

one or more leading data blocks;

a penultimate data block; and

a last data blocks;

the method comprises ordered steps of:

a) receiving a first portion of the data object, the first portion including the penultimate data block;

b) receiving a second portion of the data object, the second portion including at least one leading data block of the one or more leading data blocks;

performing cryptographic processing of penultimate data block to produce a penultimate processed data block and store a portion of the penultimate processed data block in a memory store;

d) performing cryptographic processing of at least one of the one or more leading data blocks to produce one or more processed leading data blocks; and

e) performing cryptographic processing of a concatenation of the last data block and the portion of the penultimate processed data block stored in the memory store to produce a last processed data block; and

step d) is started before step c) is completed.

19. The method of claim 18 , wherein the method is performed by a cryptographic unit comprising:

a memory store;

a hardware circuitry pipeline configured to encrypt a plaintext data block to produce a cipher text block; and

a pipeline controller configured to control the pipeline.

20. A data storage device for performing cryptographic processing of a data object to produce a processed data object, wherein:

the data object comprises a sequence of data blocks, including,

one or more leading data blocks;

a penultimate data block; and

a last data block;

the data storage device comprises means for:

a) receiving a first portion of the data object, the first portion including the penultimate data block;

b) receiving a second portion of the data object, the second portion including at least one leading data block of the one or more leading data blocks;

c) cryptographically processing the penultimate data block, to produce a penultimate processed data block, and storing a portion of the penultimate processed data block in a memory store;

d) cryptographically processing at least one of the one or more leading data blocks, to produce one or more processed leading data blocks; and

e) cryptographically processing a concatenation of the last data block and the portion of the penultimate processed data block, to produce a last processed data block,

the first portion is received before the second portion; and

step d) is started before step c) is completed.

Assignments (10)
PARTIAL RELEASE OF SECURITY INTERESTS Recorded Apr 25, 2025
From: JPMORGAN CHASE BANK, N.A., AS AGENT
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 071382/0001 →
SECURITY AGREEMENT Recorded Apr 25, 2025
From: SANDISK TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 071050/0001 →
PATENT COLLATERAL AGREEMENT Recorded Aug 23, 2024
From: SANDISK TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS THE AGENT
Reel/Frame 068762/0494 →
CHANGE OF NAME Recorded Jun 27, 2024
From: SANDISK TECHNOLOGIES, INC.
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 067982/0032 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 29, 2024
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 067567/0682 →
PATENT COLLATERAL AGREEMENT - A&R LOAN AGREEMENT Recorded Aug 21, 2023
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A.
Reel/Frame 064715/0001 →
PATENT COLLATERAL AGREEMENT - DDTL LOAN AGREEMENT Recorded Aug 21, 2023
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A.
Reel/Frame 067045/0156 →
RELEASE OF SECURITY INTEREST AT REEL 053926 FRAME 0446 Recorded Feb 8, 2022
From: JPMORGAN CHASE BANK, N.A.
To: WESTERN DIGITAL TECHNOLOGIES, INC.
Reel/Frame 058966/0321 →
SECURITY INTEREST Recorded Sep 29, 2020
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS AGENT
Reel/Frame 053926/0446 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 18, 2020
From: SEGEV, AMIR; YOSKOVITS, YUVAL; BENISTY, SHAY
To: WESTERN DIGITAL TECHNOLOGIES, INC.
Reel/Frame 052970/0058 →
Cited By (1)
US 12,436,691