IP Library Granted Patent US 11,403,252
Granted Patent B2
US 11,403,252 · App. 17/229,565 · Granted Aug 2, 2022

Universal serial bus voltage reducing adapter

Inventors: Charles Neumann (Lake Forest, CA); Robert P. Ryan (Mission Viejo, CA)
Assignee: Western Digital Technologies, Inc.
G06F13/4282G06F1/28G06F1/3225G06F1/3296H01R31/065G06F2213/0042H01R24/62H01R2107/00H01R2201/06
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Quick Facts
Patent No.
US 11,403,252
App. No.
17/229,565
Granted
Aug 2, 2022
Kind
B2
Abstract

A method and apparatus are provided to receive a voltage at a first value at a voltage reducing adaptor, ascertain a voltage supply requirement for the memory arrangement to obtain and ascertained voltage supply requirement, reduce the voltage from the first value to the ascertained voltage supply requirement within the adaptor and supply the voltage at the ascertained voltage supply requirement to the memory arrangement.

Claims (46)

1. An arrangement, comprising:

a first connector;

a second connector;

a voltage reducing adaptor coupled between the first connector and the second connector, wherein the first connector is configured to be coupled to a first device, and the second connector is configured to be coupled to a second device;

voltage conversion circuitry disposed within the voltage reducing adaptor configured to:

accept a first voltage provided by the first device at the first connector;

ascertain a voltage supply requirement for the arrangement to obtain an ascertained voltage supply requirement;

reduce the first voltage to a second voltage meeting the ascertained voltage supply requirement; and

transmit the second voltage to the second connector, wherein the voltage conversion circuitry is configured to conserve power and reduce an amount of heat produced by the second device; and

at least two buses extending from the first connector to the second connector, each of the at least two buses configured to send and receive signals to and from the first device and the second device.

2. The arrangement of claim 1 , wherein a first bus of the at least two buses comprises a USB2 connection bus.

3. The arrangement of claim 2 , wherein a second bus of the at least two buses comprises a USB3 connection bus.

4. The arrangement of claim 1 , wherein the first connector comprises a type A or type C connector.

5. The arrangement of claim 4 , wherein the second connector comprises a type A or a type C connector.

6. The arrangement of claim 5 , wherein the first connector and the second connector comprise different connectors.

7. The arrangement of claim 1 , wherein the voltage reducing adapter comprises:

a substrate;

a series of electronic devices coupled to the substrate; and

device contacts coupled to the substrate.

8. The arrangement of claim 7 , wherein the series of electronic devices comprises integrated circuits, resistors, capacitors, or inductors.

9. A system, comprising:

a first memory device connected to the first connector of the arrangement of claim 1 ; and

a second memory device connected to the second connector of the arrangement of claim 1 .

10. A voltage reducing adaptor configured to be coupled between a first device and a second device, comprising:

a substrate;

voltage conversion circuitry coupled to the substrate and configured to:

accept a first voltage provided by the first device;

ascertain a voltage supply requirement for the second device to obtain an ascertained voltage supply requirement;

reduce the first voltage to a second voltage meeting the ascertained voltage supply requirement; and

transmit the second voltage to the second device, wherein the voltage conversion circuitry comprises integrated circuits, resistors, capacitors, or inductors; and

at least two buses coupled to the voltage conversion circuitry and the substrate.

11. The adapter of claim 10 , wherein the resistors comprises a straight line set of resistors.

12. The adapter of claim 10 , wherein the voltage conversion circuitry comprises a voltage divider circuit.

13. The adapter of claim 10 , wherein the voltage conversion circuitry comprises a series transistor.

14. The adapter of claim 10 , wherein the voltage conversion circuitry comprises a zener diode.

15. The adapter of claim 10 , wherein the adapter comprises a type A receptacle on a first end and a type A receptacle on a second end.

16. The adapter of claim 10 , wherein the adapter comprises a type C receptacle on a first end and a type C receptacle on a second end.

17. The adapter of claim 10 , wherein the adapter comprises a type A receptacle on a first end and a type C receptacle on a second end.

18. An adapter, comprising:

a substrate;

a type A receptacle coupled to a first end of the substrate;

a type C receptacle coupled to a second end of the substrate;

means to reduce voltage between the first end and the second end, wherein the means to reduce voltage is configured to receive a voltage at a first value at the type A receptacle, ascertain a voltage requirement for a device coupled to the type C receptacle; and reduce the voltage from the first value to and a second value; and

means to supply voltage at the second value to the device coupled to the type C receptacle.

19. The adapter of claim 18 , wherein the means to reduce voltage is configured to reduce the voltage based upon a state of the device coupled to the type C receptacle.

20. The adapter of claim 18 , wherein the first end comprises overmold arrangements.

Assignments (10)
PARTIAL RELEASE OF SECURITY INTERESTS Recorded Apr 25, 2025
From: JPMORGAN CHASE BANK, N.A., AS AGENT
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 071382/0001 →
SECURITY AGREEMENT Recorded Apr 25, 2025
From: SANDISK TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 071050/0001 →
PATENT COLLATERAL AGREEMENT Recorded Aug 23, 2024
From: SANDISK TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS THE AGENT
Reel/Frame 068762/0494 →
CHANGE OF NAME Recorded Jun 27, 2024
From: SANDISK TECHNOLOGIES, INC.
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 067982/0032 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 29, 2024
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 067567/0682 →
PATENT COLLATERAL AGREEMENT - DDTL LOAN AGREEMENT Recorded Aug 21, 2023
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A.
Reel/Frame 067045/0156 →
PATENT COLLATERAL AGREEMENT - A&R LOAN AGREEMENT Recorded Aug 21, 2023
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A.
Reel/Frame 064715/0001 →
RELEASE OF SECURITY INTEREST AT REEL 056285 FRAME 0292 Recorded Feb 8, 2022
From: JPMORGAN CHASE BANK, N.A.
To: WESTERN DIGITAL TECHNOLOGIES, INC.
Reel/Frame 058982/0001 →
SECURITY INTEREST Recorded May 19, 2021
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS AGENT
Reel/Frame 056285/0292 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 13, 2021
From: NEUMANN, CHARLES; RYAN, ROBERT P.
To: WESTERN DIGITAL TECHNOLOGIES, INC.
Reel/Frame 055907/0577 →