IP Library Granted Patent US 11,853,572
Granted Patent B2
US 11,853,572 · App. 17/737,877 · Granted Dec 26, 2023

Encoding-aware data routing

Inventors: Raghavendra Gopalakrishnan (Karnataka, IN); Vivek Kumar (Uttar Pradesh, IN)
Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
G06F3/064G06F3/0659G06F3/0679G06F12/0253G06F3/0604
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Quick Facts
Patent No.
US 11,853,572
App. No.
17/737,877
Granted
Dec 26, 2023
Kind
B2
Abstract

Aspects of the disclosure are directed to a storage device including a memory and a controller. The memory may include a plurality of flash memory blocks such as single level cell (SLC) blocks and multi-level cell (MLC) blocks. The controller may maintain a read count of each of the SLC blocks to determine which of the blocks contains data associated with the highest number of read commands. Based on the read commands, the controller may relocate the associated data into pages of MLC blocks that have a lower number of senses required to read the data stored in those blocks.

Claims (40)

1. A storage device, comprising:

multiple memory devices comprising a first single-level cell (SLC) block, a second SLC block, a multi-level cell (MLC) block; and

a controller coupled to the multiple memory devices, the controller configured to:

compare a first read counter to a second read counter to determine that the first read counter is greater than the second read counter, wherein the first SLC block contains first data and is associated with the first read counter, and wherein the second SLC block contains second data and is associated with the second read counter; and

in response to the determination that the first read counter is greater:

transfer the first data from the first SLC block to a first page of the MLC block, wherein the first page is selected for transfer of the first data based on: (i) the first read counter being greater than the second read counter, and (ii) the first page corresponding to fewer number of senses than a second page of the MLC block; and

transfer the second data from the second SLC block to the second page of the MLC block.

2. The storage device of claim 1 , wherein the first read counter is configured to maintain a number of read commands received for the first SLC block, and wherein the second read counter is configured to maintain a number of read commands received for the second SLC block.

3. The storage device of claim 1 , wherein the MLC block is one of a triple-level cell (TLC), a quad-level cell (QLC), or a penta-level cell (PLC).

4. The storage device of claim 1 , wherein the number of senses is indicative of a number of voltage senses for reading a corresponding page of the MLC block.

5. The storage device of claim 1 , wherein the controller is further configured to compare the first read counter to the second read counter in response to a garbage collection function.

6. The storage device of claim 5 , wherein the controller is further configured to transfer the first data and transfer the second data as part of a relocation process performed in response to the garbage collection function.

7. A storage device, comprising:

multiple memory devices comprising a first single-level cell (SLC) block, a second SLC block, a first multi-level cell (MLC) block, and a second MLC block; and

a controller coupled to the multiple memory devices, the controller configured to:

select the first MLC block for a relocation process, wherein the first MLC block contains one or more of a first data and a second data, wherein the first data is associated with a first read counter, and wherein the second data is associated with a second read counter;

compare the first read counter to the second read counter to determine that the first read counter is a greater number than the second read counter; and

in response to the determination that the first read counter is greater:

transfer the first data from the first MLC block to the first SLC block; and

transfer the second data to one of the first SLC block or the second SLC block, wherein the first SLC block is designated as a block containing data associated with the greater number.

8. The storage device of claim 7 , wherein the controller, in response to the determination that the first read counter is greater, is further configured to:

generate an indication that the first data is to be transferred from the first SLC block to a lower page of the second MLC block after being transferred to the first MLC block.

9. The storage device of claim 8 , wherein the controller is further configured to:

transfer the first data from the first SLC block to a lower page of the second MLC block; and

transfer the second data from the second SLC block to another page of the second MLC block.

10. The storage device of claim 9 , wherein the lower page is a one sense page, and wherein the other page is a more than one sense page.

11. The storage device of claim 7 , wherein the first MLC block comprises an aggregation of a third SLC block and a fourth SLC block, wherein the first read counter is associated with the third SLC block, and wherein the second read counter is associated with the fourth SLC block.

12. The storage device of claim 7 , wherein the first read counter is configured to track a number of read commands received for the first data, and wherein the second read counter is configured to track a number of read commands received for the second data.

13. The storage device of claim 7 , wherein each of the first MLC block and the second MLC block is one of a triple-level cell (TLC), a quad-level cell (QLC), or a penta-level cell (PLC).

14. The storage device of claim 7 , wherein the controller is further configured to compare the first read counter to the second read counter in response to a garbage collection function.

15. The storage device of claim 14 , wherein the controller is further configured to transfer the first data and transfer the second data as part of a relocation process performed in response to the garbage collection function.

16. A method for segregating data in a multi-level cell (MLC) block, comprising:

comparing a first read counter to a second read counter to determine that the first read counter is greater than the second read counter, wherein a first single-level cell (SLC) block contains first data and is associated with the first read counter, and wherein a second SLC block contains second data and is associated with the second read counter; and

in response to the determination that the first read counter is greater:

transferring the first data from the first SLC block to a first page of the MLC block, wherein the first page is selected for transfer of the first data based on: (i) the first read counter being greater than the second read counter, and (ii) the first page corresponding to fewer number of senses than a second page of the MLC block; and

transferring the second data from the second SLC block to the second page of the MLC block.

17. The method of claim 16 , wherein the first read counter is configured to maintain a number of read commands received for the first SLC block, and wherein the second read counter is configured to maintain a number of read commands received for the second SLC block.

18. The method of claim 16 , wherein the MLC block is one of a triple-level cell (TLC), a quad-level cell (QLC), or a penta-level cell (PLC).

19. The method of claim 16 , wherein the number of senses is indicative of a number of voltage senses for reading a corresponding page of the MLC block.

20. The method of claim 16 , wherein comparing the first read counter to the second read counter is in response to a garbage collection function.

Assignments (8)
PARTIAL RELEASE OF SECURITY INTERESTS Recorded Apr 25, 2025
From: JPMORGAN CHASE BANK, N.A., AS AGENT
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 071382/0001 →
SECURITY AGREEMENT Recorded Apr 25, 2025
From: SANDISK TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 071050/0001 →
PATENT COLLATERAL AGREEMENT Recorded Aug 23, 2024
From: SANDISK TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS THE AGENT
Reel/Frame 068762/0494 →
CHANGE OF NAME Recorded Jun 27, 2024
From: SANDISK TECHNOLOGIES, INC.
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 067982/0032 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 29, 2024
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 067567/0682 →
PATENT COLLATERAL AGREEMENT - A&R LOAN AGREEMENT Recorded Aug 21, 2023
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A.
Reel/Frame 064715/0001 →
PATENT COLLATERAL AGREEMENT - DDTL LOAN AGREEMENT Recorded Aug 21, 2023
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A.
Reel/Frame 067045/0156 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 4, 2022
From: GOPALAKRISHNAN, RAGHAVENDRA; KUMAR, VIVEK
To: WESTERN DIGITAL TECHNOLOGIES, INC.
Reel/Frame 060723/0320 →
Cited By (2)
US 12,619,533 US 12,625,800