Methods for main memory with non-volatile type memory modules, and related technologies
View Patent ↗A computing system is disclosed that includes a memory controller in a processor socket normally reserved for a processor. A plurality of non-volatile memory modules may be plugged into memory sockets normally reserved for DRAM memory modules. The non-volatile memory modules may be accessed using a data communication protocol to access the non-volatile memory modules. The memory controller controls read and write accesses to the non-volatile memory modules. The memory sockets are coupled to the processor socket by printed circuit board traces. The data communication protocol to access the non-volatile memory modules is communicated over the printed circuit board traces and through the sockets normally used to access DRAM type memory modules.
1. A method of upgrading a computer system, the method comprising:
plugging a memory controller into a processor socket, the memory controller configured to control read and write accesses to non-volatile memory modules;
plugging the non-volatile memory modules into memory module sockets, the memory module sockets being coupled to the processor socket by printed circuit board traces; and
randomly accessing the non-volatile memory modules using a data communication protocol, the data communication protocol to access the non-volatile memory modules works over the printed circuit board traces and through the memory module sockets.
2. The method of claim 1 , wherein
the printed circuit board traces are pre-existing printed circuit board traces;
the processor socket is normally reserved for a processor; and
the memory module sockets are normally reserved for dynamic random access memory modules.
3. The method of claim 1 , wherein
the non-volatile memory modules include a NOR flash electrically erasable programmable read only memory (EEPROM).
4. The method of claim 1 , wherein
the data communication protocol to access the non-volatile memory modules differs from a data communication protocol to access DRAM type memory modules.
5. The method of claim 4 , wherein
a data strobe signal changes to a status signal when a non-volatile memory module is being accessed within a memory module socket of a memory channel.
6. The method of claim 1 , further comprising:
prior to plugging a memory controller into a processor socket, removing a processor from the processor socket.
7. The method of claim 1 , further comprising:
prior to plugging the plurality of non-volatile memory modules into the memory sockets, removing a plurality of DRAM memory modules from the memory sockets.
8. A method of upgrading a computer system, the method comprising:
identifying an available processor socket from among a plurality of processor sockets;
plugging a memory controller into the identified processor socket, the memory controller capable of controlling memory modules other than dynamic random access (DRAM) memory modules;
identifying one or more memory module sockets corresponding to the identified processor socket; and
installing memory modules of a type other than dynamic random access memory modules into the identified memory module sockets.
9. The method of claim 8 , wherein
the identifying of an available processor socket includes removing a processor from the identified processor socket.
10. The method of claim 8 , wherein
the identifying of the one or more memory module sockets includes removing a plurality of dynamic random access memory modules from the memory sockets.
11. The method of claim 8 , wherein
the memory modules of a type other than dynamic random access memory modules are non-volatile memory modules.
12. The method of claim 11 , wherein
the non-volatile memory modules include a NOR flash electrically erasable programmable read only memory (EEPROM).
13. The method of claim 11 , wherein
a data communication protocol to access the non-volatile memory modules differs from a data communication protocol to access DRAM type memory modules.
14. The method of claim 13 , wherein
data strobe signals change to status signals when a non-volatile memory module is being accessed within a memory module socket of a memory channel.
15. A method of upgrading a computer system, the method comprising:
plugging a processor with a first integrated memory controller into a processor socket, the first integrated memory controller configured to control read and write accesses to non-volatile memory modules;
plugging non-volatile memory modules into memory module sockets, the memory module sockets being coupled to the processor socket by printed circuit board traces; and
randomly accessing the non-volatile memory modules using a data communication protocol, the data communication protocol to access the non-volatile memory modules works over the printed circuit board traces and through the memory module sockets.
16. The method of claim 15 , further comprising:
prior to plugging the processor with the first integrated memory controller into the processor socket, removing a processor from the processor socket; and
prior to plugging the plurality of non-volatile memory modules into the memory sockets, removing a plurality of DRAM memory modules from the memory sockets.