IP Library Granted Patent US 10,387,078
Granted Patent B1
US 10,387,078 · App. 15/920,056 · Granted Aug 20, 2019

Adaptive control of host queue depth for command submission throttling using data storage controller

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Quick Facts
Patent No.
US 10,387,078
App. No.
15/920,056
Granted
Aug 20, 2019
Kind
B1
Abstract

The present disclosure describes technologies and techniques for use by a data storage controller (such as a non-volatile memory (NVM) controller) to adaptively throttle the issuance of commands by a host to the controller. In illustrative examples, an NVM controller throttles the insertion of commands by the host into its submission queues to prevent timeouts that might otherwise occur if the NVM controller has slowed its operations (due, for example, to excessive temperatures within the NVM controller) and is thus unable to complete all issued commands within a host timeout interval. In some examples, throttling is achieved by providing the host with an adjusted head pointer set to a value to reduce the depth of the submission queue as observed by the host. Fewer commands are then sent by the host to the NVM controller via the submission queues, reducing the risk of a host timeout. NVMe examples are provided.

Claims (48)

1. A method for use by a data storage controller for controlling a data storage device based on commands issued by a host device, comprising:

determining a current queue depth for a queue used by the host device to issue commands to the data storage controller, where the host device is configured to control the issuance of the commands based on queue depth;

determining a modified queue depth for reporting to the host device that is different from the current queue depth; and

controlling the issuance of additional commands from the host device to the data storage controller by reporting the modified queue depth to the host device rather than the current queue depth.

2. The method of claim 1 ,

wherein determining the modified queue depth includes setting the modified queue depth to an effective queue depth that is lower than the current queue depth, and

wherein controlling the issuance of the additional commands includes throttling the issuance of the additional commands by reporting the effective queue depth to the host device to expose the host device to a queue depth that is lower than the current queue depth.

3. The method of claim 2 ,

wherein the queue is a submission queue with an internal head pointer, and

wherein the effective queue depth is reported to the host device using an external head pointer that is different from the internal head pointer of the submission queue.

4. The method of claim 3 , wherein determining the current queue depth includes determining the current queue depth of the submission queue based on a current value of the internal head pointer of the submission queue, a current value of an internal tail pointer of the submission queue, and a maximum queue size for the submission queue.

5. The method of claim 3 , further including determining the external head pointer based on a current internal head pointer and the effective queue depth.

6. The method of claim 3 , further including reporting the external head pointer to the host device within a completion entry to set a submission queue depth as observed by the host device to the effective queue depth.

7. The method of claim 3 , further including determining whether the current queue depth of the submission queue is the same as the effective queue depth and, if so, updating the external head pointer with each new command completion and, if not, maintaining the external head pointer at a constant value with each new command completion until the current queue depth of the submission queue is the same as the effective queue depth.

8. The method of claim 3 , further including setting the effective queue depth to a value sufficient to reduce a risk of a timeout within the host device arising due to failure of the data storage controller to complete an issued command within an allotted time limit.

9. The method of claim 8 , wherein the effective queue depth is set based on one or more of: (1) a maximum size of the submission queue; (2) a performance level that can be sustained by the data storage controller in a current operating mode; (3) a total number of submission queues; (4) a current usage level of the submission queue by the host device; (5) a maximum data transfer size of the issued command; (6) a current average data transfer size of the issued command; and (7) a timeout period used by the host device.

10. The method of claim 1 , wherein there are two or more queues, and wherein the current queue depth and the modified queue depth are determined separately for each queue.

11. The method of claim 1 , further including determining whether to throttle the host device, and wherein determining the modified queue depth and controlling the issuance of the additional commands are only performed if the host device is to be throttled.

12. The method of claim 11 , wherein determining whether to throttle the host device is based on one or more of a current temperature of the data storage controller or a current power usage of the data storage controller relative to a power allocation.

13. The method of claim 11 , wherein determining whether to throttle the host device includes determining a likelihood that a command issued to the data storage controller by the host device will not be completed by the data storage controller within a timeout interval.

14. The method of claim 11 , wherein the host device employs first and second timeout intervals and issues first commands subject to the first timeout interval and issues second commands subject to the second timeout interval or subject to no timeout interval, and wherein the host device is throttled only for the first commands but not the second commands.

15. The method of claim 11 , wherein the data storage controller advertises a throttling feature to the host device to permit the host device to permit or restrict throttling.

16. The method of claim 11 , wherein the data storage controller drips command completions to the host device during periods of throttling so the host device can detect that the data storage controller is processing commands more slowly than without throttling.

17. The method of claim 11 , wherein the data storage controller enables throttling by throttling the host device by a first amount and, if no timeouts are triggered by the host device, then throttling the host device by a second and greater amount.

18. The method of claim 11 , wherein, if the data storage controller is reset by the host device due to a timeout, throttling is disabled in the data storage controller.

19. The method of claim 1 , wherein the data storage device is a non-volatile memory (NVM) device, and wherein the data storage controller accesses the NVM device based on the commands issued to the data storage controller by the host device.

20. A data storage controller for use with a data storage device, comprising:

a processing system configured to

determine a current queue depth for a queue used by a host device to issue commands to the data storage controller, where the host device is configured to control the issuance of the commands based on queue depth,

determine a modified queue depth for reporting to the host device that is different from the current queue depth, and

control the issuance of additional commands from the host device to the data storage controller by reporting the modified queue depth to the host device rather than the current queue depth.

21. The data storage controller of claim 20 ,

wherein the processing system is configured to determine the modified queue depth by setting the modified queue depth to an effective queue depth that is lower than the current queue depth, and

wherein the processing system is configured to control the issuance of additional commands by throttling the issuance of the additional commands by reporting the effective queue depth to the host device to expose the host device to a queue depth that is lower than the current queue depth.

22. The data storage controller of claim 21 ,

wherein the queue is a submission queue with an internal head pointer, and

wherein the processing system is configured to report the effective queue depth to the host device using an external head pointer that is different from the internal head pointer of the submission queue.

23. The data storage controller of claim 22 , wherein the processing system is configured to determine the current queue depth of the submission queue based on a current value of the internal head pointer of the submission queue, a current value of an internal tail pointer of the submission queue, and a maximum queue size for the submission queue.

24. The data storage controller of claim 22 , wherein the processing system is configured to determine the external head pointer based on a current internal head pointer and the effective queue depth.

25. The data storage controller of claim 22 , wherein the processing system is configured to report the external head pointer to the host device within a completion entry to set a submission queue depth as observed by the host device to the effective queue depth.

26. The data storage controller of claim 22 , wherein the processing system is further configured to determine whether the current queue depth of the submission queue is the same as the effective queue depth and, if so, to update the external head pointer with each new command completion and, if not, to maintain the external head pointer at a constant value with each new command completion until the current queue depth of the submission queue is the same as the effective queue depth.

27. The data storage controller of claim 22 , wherein the processing system is further configured to set the effective queue depth to a value sufficient to reduce a risk of a timeout within the host device arising due to failure of the data storage controller to complete an issued command within an allotted time limit.

28. The data storage controller of claim 27 , wherein the processing system is configured to set the effective queue depth based on one or more of: (1) a maximum size of the submission queue; (2) a performance level that can be sustained by the data storage controller in a current operating mode; (3) a total number of submission queues; (4) a current usage level of the submission queue by the host device; (5) a maximum data transfer size of the issued command; (6) a current average data transfer size of the issued command; and (7) a timeout period used by the host device.

29. The data storage controller of claim 20 , wherein the data storage device is a non-volatile memory (NVM) device, and wherein the processing system is further configured to access the NVM device based on the commands issued by the host device.

30. An apparatus for use with a data storage controller, comprising:

means for determining a current queue depth for a queue used by a host device to issue commands to the data storage controller, where the host device is configured to control the issuance of the commands based on queue depth;

means for determining a modified queue depth for reporting to the host device that is different from the current queue depth; and

means for controlling the issuance of additional commands from the host device to the data storage controller by reporting the modified queue depth to the host device rather than the current queue depth.

Assignments (10)
PARTIAL RELEASE OF SECURITY INTERESTS Recorded Apr 25, 2025
From: JPMORGAN CHASE BANK, N.A., AS AGENT
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 071382/0001 →
SECURITY AGREEMENT Recorded Apr 25, 2025
From: SANDISK TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 071050/0001 →
PATENT COLLATERAL AGREEMENT Recorded Aug 23, 2024
From: SANDISK TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS THE AGENT
Reel/Frame 068762/0494 →
CHANGE OF NAME Recorded Jun 27, 2024
From: SANDISK TECHNOLOGIES, INC.
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 067982/0032 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 29, 2024
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 067567/0682 →
PATENT COLLATERAL AGREEMENT - DDTL LOAN AGREEMENT Recorded Aug 21, 2023
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A.
Reel/Frame 067045/0156 →
PATENT COLLATERAL AGREEMENT - A&R LOAN AGREEMENT Recorded Aug 21, 2023
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A.
Reel/Frame 064715/0001 →
RELEASE OF SECURITY INTEREST AT REEL 052915 FRAME 0566 Recorded Feb 8, 2022
From: JPMORGAN CHASE BANK, N.A.
To: WESTERN DIGITAL TECHNOLOGIES, INC.
Reel/Frame 059127/0001 →
SECURITY INTEREST Recorded Feb 6, 2020
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS AGENT
Reel/Frame 052915/0566 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 13, 2018
From: BENISTY, SHAY
To: WESTERN DIGITAL TECHNOLOGIES, INC.
Reel/Frame 045193/0674 →