IP Library Granted Patent US 10,366,766
Granted Patent B2
US 10,366,766 · App. 15/838,502 · Granted Jul 30, 2019

Power shaping and peak power reduction by data transfer throttling

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Quick Facts
Patent No.
US 10,366,766
App. No.
15/838,502
Granted
Jul 30, 2019
Kind
B2
Abstract

An arrangement is described used to throttle data in a connected computer device having a device configured to transmit and receive data from a host, the device comprising, a device controller configured to interact with at least memory array and a data transfer throttling arrangement, the data transfer throttling arrangement configured to measure a bandwidth threshold for the device controller and pass data through the device controller when a bandwidth of the device controller is one of at and below a threshold.

Claims (54)

1. An arrangement, comprising:

a device configured to transmit and receive data from a host, the device comprising:

a device controller configured to interact with at least a memory array; and

a data transfer throttling arrangement, the data transfer throttling arrangement configured to measure a bandwidth threshold for the device controller and pass data through the device controller when a bandwidth of the device controller is one of at and below a threshold; and

an internal counter configured to increment for an amount of the bandwidth to be consumed, wherein any consumed bandwidth is decremented by the internal counter when a read/write command is issued.

2. The arrangement according to claim 1 , further comprising:

at least one interface configured to carry transmitted data from the device to the host.

3. The arrangement according to claim 1 , further comprising:

at least one layer in the device controller configured to convert data from a digital format to an analogue format and assemble data into packets for transmission.

4. The arrangement according to claim 1 , further comprising:

at least one processor configured to perform calculations for the device controller.

5. The arrangement according to claim 3 , further comprising:

a scheduler configured to schedule activities of the device controller.

6. The arrangement according to claim 5 , further comprising:

a command fetcher connected to the at least one layer wherein the command fetcher is configured to accept commands; and

a command executor connected to the command fetcher wherein the command executor is configured to execute commands.

7. The arrangement according to claim 1 , further comprising:

a direct memory access arrangement configured to access data from the data transfer throttling arrangement.

8. The arrangement according to claim 1 , further comprising:

a flash interface module configured to interface with at least one memory array.

9. The arrangement according to claim 1 , further comprising:

at least one memory array; and

a flash interface module configured to interface with the at least one memory array.

10. The arrangement according to claim 5 , further comprising:

an error correction arrangement connected to the scheduler.

11. The arrangement according to claim 5 , further comprising:

a controller path arrangement connected to the at least one layer and the scheduler.

12. A method, comprising:

monitoring a bandwidth of one of a write operation and a read operation from a connected device to a host;

checking the bandwidth to a threshold bandwidth;

sending information from the host to the connected device when the bandwidth does not exceed the threshold; and

changing an internal counter, wherein the internal counter is incremented for an amount of the bandwidth to be consumed, wherein any consumed bandwidth is decremented by the internal counter when a read/write command is issued.

13. The method according to claim 12 , further comprising:

waiting a predetermined time for sending the information from the connected device to the host when the checking of the bandwidth to a threshold bandwidth indicates that the bandwidth would exceed the threshold such that the bandwidth used during the sending of the information does not exceed the threshold bandwidth.

14. The method according to claim 12 , further comprising:

determining if a direct memory access request is pending prior to monitoring the bandwidth from the host to the connected device.

15. A method, comprising:

monitoring a bandwidth of one of a write operation and a read operation from a connected device to a host;

checking the bandwidth to a threshold bandwidth; and

sending information from the host to the connected device when the bandwidth does not exceed the threshold, further comprising:

determining if a direct memory access request is pending prior to monitoring the bandwidth from the host to the connected device, wherein the monitoring of the bandwidth is performed only when a direct memory access request is pending.

16. A method, comprising:

monitoring a bandwidth of one of a write operation and a read operation from a connected device to a host;

checking the bandwidth to a threshold bandwidth; and

sending information from the host to the connected device when the bandwidth does not exceed the threshold, further comprising:

determining if a direct memory access request is pending prior to monitoring the bandwidth from the host to the connected device, further comprising:

determining if a reset condition is present in a host prior to monitoring the bandwidth from the host to the connected device.

17. The method according to claim 16 , wherein progressing to the determining if the direct memory access request is pending prior to monitoring the bandwidth from the connected device to the host when a reset condition does not exist.

18. An arrangement, comprising:

means for monitoring a bandwidth from a connected device to a host;

means for determining when activity in the bandwidth exceeds a threshold;

means for sending information from the connected device to the host when the bandwidth does not exceed the threshold;

means for incrementing an internal counter for an amount of bandwidth to be consumed; and

means for decrementing any consumed bandwidth when a read/write command is issued.

Assignments (11)
SECURITY AGREEMENT Recorded Apr 25, 2025
From: SANDISK TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 071050/0001 →
PARTIAL RELEASE OF SECURITY INTERESTS Recorded Apr 25, 2025
From: JPMORGAN CHASE BANK, N.A., AS AGENT
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 071382/0001 →
PATENT COLLATERAL AGREEMENT Recorded Aug 23, 2024
From: SANDISK TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS THE AGENT
Reel/Frame 068762/0494 →
CHANGE OF NAME Recorded Jun 27, 2024
From: SANDISK TECHNOLOGIES, INC.
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 067982/0032 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 29, 2024
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 067567/0682 →
PATENT COLLATERAL AGREEMENT - A&R LOAN AGREEMENT Recorded Aug 21, 2023
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A.
Reel/Frame 064715/0001 →
PATENT COLLATERAL AGREEMENT - DDTL LOAN AGREEMENT Recorded Aug 21, 2023
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A.
Reel/Frame 067045/0156 →
RELEASE OF SECURITY INTEREST AT REEL 052915 FRAME 0566 Recorded Feb 8, 2022
From: JPMORGAN CHASE BANK, N.A.
To: WESTERN DIGITAL TECHNOLOGIES, INC.
Reel/Frame 059127/0001 →
SECURITY INTEREST Recorded Feb 6, 2020
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS AGENT
Reel/Frame 052915/0566 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 16, 2018
From: BENISTY, SHAY
To: WESTERN DIGITAL TECHNOLOGIES, INC.
Reel/Frame 045076/0874 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 5, 2018
From: BENISTY, SHAY
To: WESTERN DIGITAL TECHNOLOGIES, INC.
Reel/Frame 045012/0074 →