IP Library Granted Patent US 10,636,493
Granted Patent B2
US 10,636,493 · App. 16/020,742 · Granted Apr 28, 2020

Relaxed erase parameters for block erasures in non-volatile storage media

Inventors: Niles Yang (Mountain View, CA); Pitamber Shukla (Milpitas, CA)
Assignee: Western Digital Technologies, Inc.
G11C16/16G06F11/1068G11C16/3445G11C16/3495G11C29/52G11C29/765G11C29/82
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Quick Facts
Patent No.
US 10,636,493
App. No.
16/020,742
Granted
Apr 28, 2020
Kind
B2
Abstract

Dynamic modification of health metrics for data blocks in non-volatile storage media based on erase operation loop counts. In one implementation, a method includes iteratively erasing a block of non-volatile storage media until a count of non-erasable bits satisfies criteria comprising an allowable non-erasable bits parameter, and determining that a number of iterations needed to erase the block exceeds a threshold number of iterations. The method further includes, in response to the number of iterations exceeding the threshold number of iterations, increasing the allowable non-erasable bits parameter for a subsequent erasure of the block.

Claims (50)

1. An apparatus comprising:

non-volatile storage media comprising blocks of memory bits; and

control circuitry coupled to the non-volatile storage media, wherein the control circuitry comprises:

a counter to maintain a loop count for an erasure of a block in the non-volatile storage media;

a comparator to determine that the loop count satisfied a threshold loop count for the erasure of the block; and

an adjuster to relax an erase parameter for a later erasure of the block in response to the loop count having satisfied the threshold loop count for the erasure;

wherein the block comprises segments, and wherein the adjuster, in response to the loop count having satisfied the threshold loop count for the erasure, determines that a quantity of segments unavailable for storing data satisfies a segment criteria and, in response to the quantity of segments satisfying the segment criteria, increases a data scrubbing priority for the block.

2. The apparatus of claim 1 wherein the erase parameter comprises an allowable non-erasable bits value and wherein to relax the erase parameter for the later erasure of the block, the adjuster increases the allowable non-erasable bits value for a next erasure of the block.

3. The apparatus of claim 2 wherein the adjuster, in response to the loop count having satisfied the threshold loop count for the erasure, identifies a segment having a largest quantity of non-erasable bits and marks the segment as no longer available for storing data.

4. The apparatus of claim 1 wherein the adjuster, in response to the quantity of segments unavailable for storing data satisfying the segment criteria, changes a classification for the block from available hot storage to available cold storage.

5. The apparatus of claim 1 wherein the adjuster monitors a lifespan of the non-volatile storage media and triggers the comparator to determine that the loop count satisfied the threshold loop count when the non-volatile storage media reaches a mid-point in the lifespan.

6. The apparatus of claim 1 wherein the erasure comprises a program erase operation on cells in the block that store bits.

7. A storage device comprising:

non-volatile storage media comprising memory blocks; and

a controller configured to:

track a loop count for an erasure of one or more of the memory blocks;

after the erasure, determine that the loop count for the erasure did not exceed a threshold loop count for the erasure;

in response to determining that the loop count did not exceed the threshold loop count, reduce an allowed non-erasable bits parameter for a subsequent erasure of the one or more memory blocks;

identify one or more word-lines of a plurality of word-lines in a block of the one or more memory blocks as having a cluster of non-erasable bits that satisfies at least one criterion; and

designate the one or more word-lines as read-only.

8. The storage device of claim 7 wherein the controller is further configured to:

determine that a loop count for a previous erasure of a block of memory cells exceeded the threshold loop count; and

increase the allowable non-erasable bits threshold for the block of memory cells in response to the loop count having exceeded the threshold loop count.

9. The storage device of claim 7 wherein the controller is further configured to, in response to the loop count exceeding the threshold loop count, determine that a quantity of word-lines unavailable for storing data in the block satisfies word-line criteria, and in response to the quantity of word-lines unavailable for storing data in the block satisfying the word-line criteria, change a classification for the block from hot storage to cold storage.

10. The storage device of claim 9 wherein the controller is further configured to, in response to the quantity of word-lines unavailable for storing data in the in the block satisfying the word-line criteria, increase a data scrubbing priority for the block.

11. The apparatus of claim 7 wherein the erasure of a block of the one or more memory blocks comprises a program erase operation on the memory cells for the block.

12. A computing apparatus comprising:

a host processing system; and

a storage system coupled to the host processing system and configured to:

receive a trim command from the host processing system to initiate an erasure of a block of non-volatile storage media;

in response to the trim command, erase the block of the non-volatile storage media based on an allowable non-erasable bits value; and

modify the allowable non-erasable bits value for a subsequent erasure of the block in response to a loop count for the erasure having met at least one criterion;

wherein:

the block comprises segments,

the storage system is further configured to:

in response to the loop count meeting the at least one criterion, determine that a quantity of segments unavailable for storing data satisfies segment criteria, and

in response to the quantity of segments satisfying the segment criteria, increase a data scrubbing priority for the block.

13. The computing apparatus of claim 12 wherein to modify the allowable non-erasable bits value, the storage system increases the allowable non-erasable bits value for the subsequent erasure of the block.

14. The computing apparatus of claim 12 wherein to modify the allowable non-erasable bits value, the storage system decreases the allowable non-erasable bits value for the subsequent erasure of the block.

15. The computing apparatus of claim 12 wherein the storage system is further configured to, in response to the loop count meeting the at least one criterion, identify a segment of the block having a largest quantity of non-erasable bits, and designate the segment as no longer available for storing data.

16. An apparatus comprising:

a means for iteratively erasing a block of non-volatile storage media until a count of non-erasable bits satisfies an allowable non-erasable bits threshold;

a means for determining that a number of iterations needed to erase the block exceeds a threshold number of iterations; and

a means for increasing the allowable non-erasable bits value for at least one subsequent erasure of the block in response to the number of iterations exceeding the threshold number of iterations;

wherein:

the block comprises word-lines, and

the apparatus further comprises means for identifying at least one of the word-lines within which the non-erasable bits are clustered and marking the one of the word-lines as unavailable for writing data.

17. The apparatus of claim 16 further comprising:

a means for determining that the number of iterations needed to erase the block falls below the threshold number of iterations; and

a means for, in response to the number of iterations falling below the threshold number of iterations, decreasing the allowable non-erasable bits value for at least one subsequent erasure of the block.

Assignments (10)
PARTIAL RELEASE OF SECURITY INTERESTS Recorded Apr 25, 2025
From: JPMORGAN CHASE BANK, N.A., AS AGENT
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 071382/0001 →
SECURITY AGREEMENT Recorded Apr 25, 2025
From: SANDISK TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 071050/0001 →
PATENT COLLATERAL AGREEMENT Recorded Aug 23, 2024
From: SANDISK TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS THE AGENT
Reel/Frame 068762/0494 →
CHANGE OF NAME Recorded Jun 27, 2024
From: SANDISK TECHNOLOGIES, INC.
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 067982/0032 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 29, 2024
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 067567/0682 →
PATENT COLLATERAL AGREEMENT - DDTL LOAN AGREEMENT Recorded Aug 21, 2023
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A.
Reel/Frame 067045/0156 →
PATENT COLLATERAL AGREEMENT - A&R LOAN AGREEMENT Recorded Aug 21, 2023
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A.
Reel/Frame 064715/0001 →
RELEASE OF SECURITY INTEREST AT REEL 052915 FRAME 0566 Recorded Feb 8, 2022
From: JPMORGAN CHASE BANK, N.A.
To: WESTERN DIGITAL TECHNOLOGIES, INC.
Reel/Frame 059127/0001 →
SECURITY INTEREST Recorded Feb 6, 2020
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS AGENT
Reel/Frame 052915/0566 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 27, 2018
From: YANG, NILES; SHUKLA, PITAMBER
To: WESTERN DIGITAL TECHNOLOGIES, INC.
Reel/Frame 046221/0382 →