Memory apparatus for replaceable non-volatile memory
View Patent ↗In one embodiment of the invention, a replaceable memory apparatus is disclosed. The replaceable memory apparatus includes a first rectangular multilayer printed circuit board having a first side and a second side opposite the first side; a first male pluggable electrical connector mounted to the first side near a first edge; a first female pluggable electrical connector mounted to the second side; and first non-volatile memory mounted to the first side and the second side. The first female pluggable electrical connector is coupled to the first male pluggable electrical connector to feed through first signals. The first non-volatile memory is coupled to the first female pluggable electrical connector and the first male pluggable electrical connector to receive the first signals.
1. A memory apparatus comprising:
a baseboard printed circuit board including
a host edge connector adapted to couple the baseboard to a host system;
a master controller including a host bus channel coupled to the host edge connector and a plurality of memory bus channels;
a plurality of slave controllers coupled to the master controller, the plurality of slave controllers adapted to provide transparent access to non-volatile memory;
a first plurality of daughter-card sockets respectively coupled to the plurality of memory bus channels, the first plurality of sockets adapted to receive a plurality of daughter-memory-cards;
one or more first replaceable daughter-memory-cards removeably plugged into the first plurality of daughter-card sockets, each of the first replaceable daughter-memory-cards including a plurality of packaged non-volatile memory mounted to the replaceable daughter-memory-card; and
a non-volatile card configuration device coupled to the master controller; and
wherein the master controller natively controls the non-volatile memory to obtain predictable bandwidth and latency performance with the non-volatile memory mounted to the replaceable daughter-memory-cards.
2. The memory apparatus of claim 1 , wherein
the plurality of slave controllers are mounted to the baseboard and coupled between the master controller and the plurality of daughter-card sockets.
3. The memory apparatus of claim 1 , wherein
the plurality of slave controllers are mounted together in an integrated circuit package with the master controller and coupled between the master controller and the plurality of daughter-card sockets.
4. The memory apparatus of claim 1 , wherein
the plurality of slave controllers are mounted to the plurality of daughter-memory-cards coupled between the master controller and the plurality of packaged non-volatile memory.
5. The memory apparatus of claim 1 , wherein
each slave controller to
arbitrate the memory bus channels shared by multiple non-volatile memory devices;
to buffer and multiplex signals between the master controller and the multiple non-volatile memory devices, and
to combine a sequence of predictable non-volatile memory operations together into a compound operation to improve control bandwidth.
6. The memory apparatus of claim 1 , further comprising:
one or more second replaceable daughter-memory-cards removeably plugged into the one or more first replaceable daughter-memory-cards, each of the second replaceable daughter-memory-cards including a plurality of packaged non-volatile memory mounted to the second replaceable daughter-memory-card.
7. The memory apparatus of claim 1 , wherein one daughter-memory-card is removeably plugged into one socket, and the memory apparatus further includes
one or more daughter-memory-cards removeably plugged into one or more sockets of the baseboard.
8. The memory apparatus of claim 1 , further comprising:
a plurality of capacitors mounted to the baseboard to store power; and
power failure circuitry mounted to the baseboard and coupled to the edge connector to receive slot power and ground, and to the plurality of capacitors to receive capacitor power and ground;
wherein the power failure circuitry is further coupled to the master controller, the plurality of slave controllers, the plurality of daughter-card sockets and daughter-memory-cards coupled thereto, and the non-volatile card configuration device, the power failure circuitry to provide either slot power or capacitor power thereto;
wherein the power failure circuitry to detect a slot power failure, switch from supplying slot power to provide capacitor power, and notify the master controller and the plurality of slave controllers to switch into a power failure mode to execute data preservation operations.
9. The memory apparatus of claim 8 , wherein
upon initial power up, the power failure circuitry to charge the plurality of capacitors before the master controller and the plurality of slave controllers permit access to non-volatile memory in the daughter-memory-cards.
10. The memory apparatus of claim 1 , further comprising:
a read only memory (ROM) mounted to the baseboard, the ROM to store boot instructions for the memory apparatus;
a non-volatile (NV) memory mounted to the baseboard, the NV memory to allow upgrade of firmware instructions to drive master and slave controllers and maintain translation structures needed to store or access data;
a dynamic read only memory (DRAM) mounted to the baseboard, the DRAM to provide scratch pad memory;
an embedded processor mounted to the baseboard and coupled to the ROM, the NV memory, the DRAM, and the master controller, wherein the embedded processor is in communication with the host to execute the firmware instructions to drive and control the master and slave controllers and maintain translation structures needed to store or access data in response to host application or operating system software requests.
11. The memory apparatus of claim 1 , further comprising:
a host driver stored in a host storage device, the host driver including instructions executed by a host processor using translation structures stored in a host memory to drive and control the master and slave controllers to store or access data in response to application or operating system software requests.
12. A memory apparatus comprising:
a baseboard printed circuit board including
a host edge connector adapted to couple the baseboard to a host system;
a master controller including a host bus channel coupled to the host edge connector and a plurality of memory bus channels;
a plurality of slave controllers coupled to the master controller, the plurality of slave controllers adapted to provide transparent access to non-volatile memory;
a first plurality of daughter-card sockets respectively coupled to the plurality of memory bus channels, the first plurality of sockets adapted to receive a plurality of daughter-memory-cards;
one or more first replaceable daughter-memory-cards removeably plugged into the first plurality of daughter-card sockets, each of the first replaceable daughter-memory-cards including a plurality of packaged non-volatile memory mounted to the replaceable daughter-memory-card;
a plurality of capacitors mounted to the baseboard to store power; and
power failure circuitry mounted to the baseboard and coupled to the edge connector to receive slot power and ground, and to the plurality of capacitors to receive capacitor power and ground;
wherein the power failure circuitry is further coupled to the master controller, the plurality of slave controllers, the plurality of daughter-card sockets and daughter-memory-cards coupled thereto, and the non-volatile card configuration device, the power failure circuitry to provide either slot power or capacitor power thereto.
13. The memory apparatus of claim 12 , wherein
the power failure circuitry to detect a slot power failure, switch from supplying slot power to provide capacitor power, and notify the master controller and the plurality of slave controllers to switch into a power failure mode to execute data preservation operations.
14. The memory apparatus of claim 12 , wherein
upon initial power up, the power failure circuitry to charge the plurality of capacitors before the master controller and the plurality of slave controllers permit access to non-volatile memory in the daughter-memory-cards.
15. A memory apparatus comprising:
a baseboard printed circuit board including
a host edge connector adapted to couple the baseboard to a host system;
a master controller including a host bus channel coupled to the host edge connector and a plurality of memory bus channels;
a plurality of slave controllers coupled to the master controller, the plurality of slave controllers adapted to provide transparent access to non-volatile memory;
a first plurality of daughter-card sockets respectively coupled to the plurality of memory bus channels, the first plurality of sockets adapted to receive a plurality of daughter-memory-cards;
one or more first replaceable daughter-memory-cards removeably plugged into the first plurality of daughter-card sockets, each of the first replaceable daughter-memory-cards including a first plurality of packaged non-volatile memory mounted to the replaceable daughter-memory-card; and
one or more second replaceable daughter-memory-cards removeably plugged into the one or more first replaceable daughter-memory-cards, each of the second replaceable daughter-memory-cards including a second plurality of packaged non-volatile memory mounted to the second replaceable daughter-memory-card.
16. The memory apparatus of claim 15 , wherein
each of the first replaceable daughter-memory cards includes
a first rectangular multilayer printed circuit board having a first side and a second side opposite the first side;
a first pluggable electrical connector mounted to the first side near a first edge; and
a second pluggable electrical connector mounted to the second side, the second pluggable electrical connector coupled to the first pluggable electrical connector to feed through first signals from the first replaceable daughter-memory cards to the second replaceable daughter-memory cards;
and
each of the second replaceable daughter-memory cards includes
a second rectangular multilayer printed circuit board having a first side and a second side opposite the first side; and
a third pluggable electrical connector mounted to the first side near a first edge, the third pluggable electrical connector to couple to the second pluggable electrical connector to receive the first signals.
17. The memory apparatus of claim 15 , wherein
each of the first replaceable daughter-memory cards includes
a first rectangular multilayer printed circuit board having a first side and a second side opposite the first side;
a first pluggable electrical connector mounted to the first side near a first edge;
a second pluggable electrical connector mounted to the second side, the second pluggable electrical connector coupled to the first pluggable electrical connector to feed through first signals from the first replaceable daughter-memory cards to the second replaceable daughter-memory cards;
a third pluggable electrical connector mounted to the first side near a second edge opposite the first edge; and
a fourth pluggable electrical connector mounted to the second side, the fourth pluggable electrical connector coupled to the third pluggable electrical connector to feed through second signals from the first replaceable daughter-memory cards to the second replaceable daughter-memory cards;
and
each of the second replaceable daughter-memory cards includes
a second rectangular multilayer printed circuit board having a first side and a second side opposite the first side;
a fifth pluggable electrical connector mounted to the first side near a first edge, the fifth pluggable electrical connector to couple to the second pluggable electrical connector to receive the first signals; and
a sixth pluggable electrical connector mounted to the first side near a second edge opposite the first edge, the sixth pluggable electrical connector to couple to the fourth pluggable electrical connector to receive the second signals.
18. The memory apparatus of claim 15 , further comprising:
a plurality of capacitors mounted to the baseboard to store power;
power failure circuitry mounted to the baseboard and coupled to the edge connector to receive slot power and ground, and to the plurality of capacitors to receive capacitor power and ground;
wherein the power failure circuitry is further coupled to the master controller, the plurality of slave controllers, the plurality of daughter-card sockets and daughter-memory-cards coupled thereto, and the non-volatile card configuration device, the power failure circuitry to provide either slot power or capacitor power thereto;
wherein the power failure circuitry to detect a slot power failure, switch from supplying slot power to provide capacitor power, and notify the master controller and the plurality of slave controllers to switch into a power failure mode to execute data preservation operations.
19. The memory apparatus of claim 18 , wherein upon initial power up,
the power failure circuitry to charge the plurality of capacitors before the master controller and the plurality of slave controllers permit access to non-volatile memory in the daughter-memory-cards.