Buffering storage device data in a host memory buffer
Apparatus, systems, methods, and computer program products for buffering storage device data in a host memory buffer (HMB) are presented. A non-volatile memory and a controller are in communication with a non-volatile memory. A controller is configured to receive an input/output (I/O) operation including data. A controller is configured to transmit at least a portion of data to an HMB of a host device separate from a non-volatile memory and a controller for storage until a trigger event occurs.
1. An apparatus comprising:
a non-volatile memory; and
a controller in communication with the non-volatile memory, wherein the controller is configured to:
receive an input/output (I/O) request including first data, and
transmit at least a portion of the first data to a host memory buffer (HMB) of a host device separate from the non-volatile memory and the controller for storage until a trigger event occurs, the I/O request is a read request, the portion of the first data includes metadata associated with second data to be read from the non-volatile memory and the trigger event comprises determining that the controller is available to receive the second data, the metadata includes TASK ID information and data path configuration information for reading the second data by the host device.
2. The apparatus of claim 1 , wherein:
the host device includes a first data transfer speed greater than a second transfer speed for the controller.
3. The apparatus of claim 1 , wherein in response to the trigger event occurring, the controller is further configured to facilitate erasing the portion of the first data from the HMB.
4. The apparatus of claim 1 , wherein the portion of the first data stored in the HMB comprises a size of at least two word lines worth of data.
5. The apparatus of claim 1 , wherein:
the controller comprises a transfer random access memory (TRAM);
and
the trigger event comprises determining that the TRAM includes an available amount of storage space sufficient to store the portion of the first data stored in the HMB.
6. The apparatus of claim 5 , wherein:
in response to the trigger event, the controller is further configured to transmit the portion of the first data stored in the HMB to the TRAM.
7. The apparatus of claim 1 , wherein:
the controller includes a first data transfer speed greater than a second transfer speed for the host device.
8. The apparatus of claim 7 , wherein:
in response to the trigger event, the controller is further configured to transmit the portion of the first data from the HMB to the host device.
9. The apparatus of claim 1 , wherein:
the metadata in the HMB is managed using a first-in-first-out (FIFO) queue.
10. The apparatus of claim 9 , wherein:
the controller comprises a transfer random access memory (TRAM);
in response to the trigger event, the controller is further configured to transmit the portion of the first data from the non-volatile memory to the TRAM; and
the controller is further configured to transmit the portion of the first data from the TRAM to the host device.
11. A method, comprising:
receiving, by a controller, a read command associated with first data from a host device; and
transmitting at least a portion of the first data from the controller to a host memory buffer (HMB) of the host device for at least temporary storage until a trigger event occurs, wherein the host device and the HMB are separate from the controller, the portion of the first data includes metadata associated with second data to be read from a non-volatile memory, the trigger event comprises determining that a transfer random access memory (TRAM) of the controller is available to receive the second data, the metadata includes TASK ID information and data path configuration information for reading the second data by the host device.
12. The method of claim 11 , wherein:
the method further comprises erasing the first data from the HMB in response to the trigger event.
13. The method of claim 11 , wherein:
the host device includes a first data transfer speed greater than a second transfer speed for the controller.
14. The method of claim 11 , wherein:
the controller includes a first data transfer speed greater than a second data transfer speed for the host device;
and
the method further comprises, in response to the trigger event:
transmitting the first data from the HMB to the TRAM, and
reading the first data from the TRAM to the host device.
15. The method of claim 11 , wherein:
the metadata in the HMB is managed using a first-in-first-out (FIFO) queue.
16. A system, comprising:
a host device including a host memory buffer (HMB); and
a non-volatile memory in communication with the host device, the non-volatile memory including a controller comprising:
an input/output (I/O) circuit configured to receive an I/O operation comprising first data from the host device, the I/O operation comprises a read operation, and
a transfer circuit configured to transmit at least a portion of the first data to the HMB until a trigger event occurs, the portion of the first data includes metadata associated with second data to be read from the non-volatile memory and the trigger event comprises determining that the controller is available to receive the second data, the metadata includes TASK ID information and data path configuration information for reading the second data by the host device.
17. The system of claim 16 , wherein:
the controller further comprises an erase circuit configured to erase the first data from the HMB in response to the trigger event.
18. An apparatus, comprising:
a non-volatile memory; and
a controller in communication with the non-volatile memory, the controller includes means for receiving a read request for first data from a host device and means for transmitting at least a portion of the first data to a host memory buffer (HMB) of the host device separate from the non-volatile memory and the controller for storage until a trigger event occurs, the portion of the first data includes metadata associated with second data to be read from the non-volatile memory and the trigger event comprises determining that the controller is available to receive the second data, the metadata includes TASK ID information and data path configuration information for reading the second data by the host device.
19. The apparatus of claim 18 , wherein:
the host device includes a first data transfer speed that is less than a second transfer speed for the controller.
20. The apparatus of claim 18 , wherein:
the controller comprises a transfer random access memory (TRAM); and
the trigger event comprises determining that the TRAM includes an available amount of storage space sufficient to store the portion of the first data stored in the HMB.